BT815A Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Fabricante

BT815A

VideoStream™ Decoders

Unspecified 

Bt819A/7A/5A

FUNCTIONAL DESCRIPTION

Pin Descriptions

Table 2. Pin Descriptions Grouped By Pin Function (4 of 6)

Pin # I/O Pin Name

Description

2–9

O VD[15:8]

22–29 O VD[7:0]

84

O DVALID

87

O AEF

NC

86

O AFF

NC

91

I

CLKIN

G GND

88

I

FRST

P VDD

Digitized Video Data Outputs (TTL Compatible). VD0 is the least significant bit of

the bus in 16-bit mode. VD8 is the least significant bit of the bus in 8-bit mode.

In SPI mode: the information is output with respect to CLKx1 in 16-bit mode,

and CLKx2 in 8-bit mode. In SPI mode 2, this port is configured to output control

codes as well as data.

In API mode: this port may be used only in 16-bit mode with VD0 as the least

significant bit. The data is output with respect to CLKIN. In API mode, control codes

for HRESET and VRESET are always inserted into the data stream.

Data Valid Output (TTL Compatible).

In SPI mode: this pin indicates if a valid pixel is being output onto the data bus.

The Bt819A digitizes video at eight times the subcarrier rate, and outputs scaled

video. Therefore, there are more clocks than valid data. DVALID indicates when

valid pixel data is being output.

In API mode: DVALID performs a different function. It toggles high when the

FIFO has 20 locations filled, and remains high until the FIFO is empty. It can be

used to control FIFO reads for bursting information out of the FIFO. DVALID may

be programmed to toggle when almost full (32 pixels). In API mode, DVALID indi-

cates valid data in the FIFO, which includes both pixel information and control

codes.

Note: The polarity of this pin is programmable through the VPOLE register.

The FIFO Pins (Bt819A Only)

Almost Empty Flag. Indicates when there are less than 9 pixels in the FIFO. Note:

The AEF flag is pipelined to the output of the chip. Also, the FIFO is being written

into during this time. Therefore, the actual number of pixels in the FIFO when AEF

toggles will vary. The number of pixels remaining could be as low as 2. The system

should stop reading from the FIFO as soon as AEF indicates almost empty. See

Figure 28 for a recommended circuit.

No Connect on Bt817A and Bt815A.

Almost Full Flag. Indicates when there are more than 32 FIFO locations full. It can

also be programmed to signal a half full condition (with 20 locations full).

Note: The polarity of this pin is programmable through the VPOLE register.

No Connect on Bt817A and Bt815A.

Asynchronous FIFO output clock (TTL compatible). This asynchronous clock is

used to output data onto the VD15-VD0 bus and other VTU control signals. CLKX2

or CLKX1 outputs of the Bt819A can be tied to this pin. When using the Bt819A in

SPI mode, CLKIN must be pulled low.

Ground for digital circuitry on Bt817A and Bt815A.

FIFO Reset (TTL compatible). A logical 0 on this pin asynchronously resets the

read and write address pointers to zero. When using the Bt819A in SPI mode,

FRST must be pulled high.

Power supply for digital circuitry on Bt817A and Bt815A.

9

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