BR34E02FVT-3,BR34E02NUX-3
●Synchronous Data Timing
Technical Note
SCL
SDA
(IN)
SDA
(OUT)
tHD:STA
tBUF
tR
tF
tHIGH
tSU:DAT tLOW
tPD
tHD:DAT
tDH
SCL
DATA(1)
SDA D1 D0 ACK
WP
tSU:WP
DATA(n)
ACK
tWR
STOP BIT
tHD:WP
Fig.1-(a) Synchronous Data Timing
○ SDA data is latched into the chip at the rising edge
○ of SCL clock.
○ Output data toggles at the falling edge of SCL clock.
Fig.1-(d) WP Timing Of The Write Operation
SCL
tSU:STA
SDA
tHD:STA
tSU:STO
START BIT
SCL
SDA
DATA(1)
D1 D0 ACK
DATA(n)
WP
STOP BIT
tHIGH : WP
ACK
tWR
Fig.1-(b) Start/Stop Bit Timing
Fig.1-(e) WP Timing Of The Write Cancel Operation
SCL
SDA
D0
WRITE DATA(n)
ACK
tWR
STOP
CONDITION
START
CONDITION
Fig.1-(c) Write Cycle Timing
○For WRITE operation, WP must be "Low" from the rising edge of
the clock (which takes in D0 of first byte) until the end of tWR.
(See Fig.1-(d) ) During this period, WRITE operation can be
canceled by setting WP "High".(See Fig.1-(e))
○When WP is set to "High" during tWR, WRITE operation is
immediately ceased, making the data unreliable. It must then
be re-written.
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3/19
2011.11 - Rev.A