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BR34E02-W

Double-cell Memory for Plug & Play DDR/DDR2 (For memory module) SPD Memory

ROHM Semiconductor 

●Write Protect Cycle

S

W

T

R

A

I

R

SLAVE

T

T

ADDRESS E

W ORD

ADDRESS

SDA

L IN E

0 1 1 0 A 2A 1A 0

*

**

DATA

S

T

O

P

*

RA

A

A

WP

/C

WK

C

K

C

K

*:DO N’T CARE

Fig. 38 Permanent Write Protect Cycle

・Permanent set Write Protect command set data of 00h～7Fh in 256 words write protection block. Clear Write Protect

command can cancel write protection block which is set by set write Protect command. Cancel of write protection

block which is set by permanent set Write Protect command at once is impossibility. When these commands are

carried out, WP pin must be OPEN or GND.

・Permanent Set Write Protect command needs tWR from stop condition same as Byete Write and Page Write,

During tWR, input command is canceled.

・Refer to P8/19 about reply of ACK in each protect state.

S

W

T

R

A

I

R

SLAVE

T

T

ADDRESS E

W ORD

ADDRESS

SDA

L IN E

0 11 0 0 01

*

**

RA

A

/C

C

WP

WK

K

DATA

S

T

O

P

*

A

C

K

*:DO N’T CARE

Fig. 39 Set Write Protect Cycle

・Permanent set Write Protect command set data of 00h～7Fh in 256 words write protection block. Clear Write Protect

command can cancel write protection block which is set by set write Protect command. Cancel of write protection

block which is set by permanent set Write Protect command at once is impossibility. When these commands are

carried out, WP pin must be OPEN or GND.

・Permanent Set Protect command needs tWR from stop condition same as Byete Write and Page Write, During tWR,

input command is canceled.

・Refer to P8/19 about reply of ACk in each protect state.

11/19

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