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ATTINY88-CCU Datasheet PDF : 298 Pages
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4.5.1
The X-register, Y-register, and Z-register
The registers R26:R31 have some added functions to their general purpose usage. These regis-
ters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 4-3.
Figure 4-3. The X-, Y-, and Z-registers
15
XH
XL
0
X-register
7
07
0
R27 (0x1B)
R26 (0x1A)
15
YH
YL
0
Y-register
7
07
0
R29 (0x1D)
R28 (0x1C)
Z-register
15
ZH
7
0
R31 (0x1F)
ZL
0
7
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
4.6 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer should be set to
point to RAMEND. The Stack Pointer is decremented by one when data is pushed onto the
Stack with the PUSH instruction, and it is decremented by two when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by two when
data is popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
15
SP15
SP7
7
R/W
R/W
RAMEND
RAMEND
14
SP14
SP6
6
R/W
R/W
RAMEND
RAMEND
13
SP13
SP5
5
R/W
R/W
RAMEND
RAMEND
12
SP12
SP4
4
R/W
R/W
RAMEND
RAMEND
11
SP11
SP3
3
R/W
R/W
RAMEND
RAMEND
10
SP10
SP2
2
R/W
R/W
RAMEND
RAMEND
9
SP9
SP1
1
R/W
R/W
RAMEND
RAMEND
8
SP8
SP0
0
R/W
R/W
RAMEND
RAMEND
SPH
SPL
12 ATtiny48/88
8008F–AVR–06/10
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