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ATTINY20-EK1

8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash

Atmel Corporation 

4.7 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a

separate Program Vector in the program memory space. All interrupts are assigned individual enable bits which must be

written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The

complete list of vectors is shown in “Interrupts” on page 36. The list also determines the priority levels of the different

interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the

External Interrupt Request 0.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software

can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt

routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these

interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling

routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one

to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.

Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding

Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by

order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily

have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be

triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before

any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning

from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be

executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending

interrupts, as shown in the following example.

Assembly Code Example

sei

sleep

pending interrupt(s)

Note: See “Code Examples” on page 7.

; set Global Interrupt Enable

; enter sleep, waiting for interrupt

; note: will enter sleep before any

4.7.1

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles

the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the

Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes

three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before

the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is

increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter

(two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

ATtiny20 [DATASHEET] 12

Atmel-8235F-AVR-ATtiny20-Datasheet_09/2014

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