ATTINY12(2003) Ver la hoja de datos (PDF) - Atmel Corporation
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ATTINY12 Datasheet PDF : 91 Pages
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ATtiny11/12
Interrupt Handling
Interrupt Response Time
General Interrupt Mask
Register – GIMSK
1. When BOD is enabled (by programming the BODEN fuse)
2. When the bandgap reference is connected to the Analog Comparator (by setting
the AINBG bit in ACSR)
Thus, when BOD is not enabled, after setting the AINBG bit, the user must always allow
the reference to start up before the output from the Analog Comparator is used. The
bandgap reference uses approximately 10 µA, and to reduce power consumption in
Power-down mode, the user can turn off the reference when entering this mode.
The ATtiny11/12 has two 8-bit Interrupt Mask control registers; GIMSK – General Inter-
rupt Mask register and TIMSK – Timer/Counter Interrupt Mask register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction – RETI – is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag
bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for
as long as the interrupt condition is active.
Note that the status register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles
minimum. After the 4 clock cycles, the program vector address for the actual interrupt
handling routine is executed. During this 4-clock-cycle period, the Program Counter (9
bits) is pushed onto the Stack. The vector is normally a relative jump to the interrupt rou-
tine, and this jump takes 2 clock cycles. If an interrupt occurs during execution of a
multi-cycle instruction, this instruction is completed before the interrupt is served. In
ATtiny12, if an interrupt occurs when the MCU is in Sleep mode, the interrupt response
time is increased by 4 clock cycles.
A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock
cycles, the Program Counter (9 bits) is popped back from the Stack, and the I-flag in
SREG is set. When AVR exits from an interrupt, it will always return to the main program
and execute one more instruction before any pending interrupt is served.
Bit
7
6
5
4
$3B
-
INT0
PCIE
-
Read/Write
R
R/W
R/W
R
Initial Value
0
0
0
0
3
2
1
0
-
-
-
-
GIMSK
R
R
R
R
0
0
0
0
25
1006D–AVR–07/03
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