ATMEGA6450V-8AJ Ver la hoja de datos (PDF) - Atmel Corporation
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ATMEGA6450V-8AJ Datasheet PDF : 347 Pages
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level of the internal BOD does not match the needed detection level, an external low
VCC reset Protection circuit can be used. If a reset occurs while a write operation is in
progress, the write operation will be completed provided that the power supply voltage is
sufficient.
I/O Memory
The I/O space definition of the ATmega325/3250/645/6450 is shown in “Register Sum-
mary” on page 325.
All ATmega325/3250/645/6450 I/Os and peripherals are placed in the I/O space. All I/O
locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transfer-
ring data between the 32 general purpose working registers and the I/O space. I/O
Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI
and CBI instructions. In these registers, the value of single bits can be checked by using
the SBIS and SBIC instructions. Refer to the instruction set section for more details.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F
must be used. When addressing I/O Registers as data space using LD and ST instruc-
tions, 0x20 must be added to these addresses. The ATmega325/3250/645/6450 is a
complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O
space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions
can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike
most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and
can therefore be used on registers containing such Status Flags. The CBI and SBI
instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
General Purpose I/O Registers
The ATmega325/3250/645/6450 contains three General Purpose I/O Registers. These
registers can be used for storing any information, and they are particularly useful for
storing global variables and Status Flags. General Purpose I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and
SBIC instructions.
General Purpose I/O Register
2 – GPIOR2
Bit
7
6
5
4
3
2
1
0
MSB
LSB
GPIOR2
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
General Purpose I/O Register
1 – GPIOR1
Bit
7
6
5
4
3
2
1
0
MSB
LSB
GPIOR1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
General Purpose I/O Register
0 – GPIOR0
Bit
7
6
5
4
3
2
1
0
MSB
LSB
GPIOR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
24 ATmega325/3250/645/6450
2570A–AVR–09/04
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