ATMEGA64 Ver la hoja de datos (PDF) - Atmel Corporation
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ATMEGA64 Datasheet PDF : 363 Pages
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ATmega64(L)
Overview
The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing
the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
PF0 - PF7
VCC
GND
AVCC
PORTF DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
PA0 - PA7
PORTA DRIVERS
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
PC0 - PC7
PORTC DRIVERS
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
AGND
AREF
PEN
JTAG TAP
ON-CHIP DEBUG
BOUNDARY-
SCAN
PROGRAMMING
LOGIC
ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
CALIB. OSC
OSCILLATOR
OSCILLATOR
TIMING AND
CONTROL
8-BIT DATA BUS
XTAL1
XTAL2
RESET
STATUS
REGISTER
USART0
SPI
USART1
2-WIRE SERIAL
INTERFACE
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
PORTE DRIVERS
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
PORTB DRIVERS
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
PORTD DRIVERS
DATA REG. DATA DIR.
PORTG REG. PORTG
PORTG DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
3
2490G–AVR–03/04
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