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ATMEGA165-16AJ Ver la hoja de datos (PDF) - Atmel Corporation

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ATMEGA165-16AJ Datasheet PDF : 19 Pages
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Port G (PG4..PG0)
RESET
XTAL1
XTAL2
AVCC
AREF
tors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset
occurs.
Port F also serves the functions of the JTAG interface.
Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port G output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port G pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features of the ATmega165 as listed
on page 63.
Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
16 on page 38. Shorter pulses are not guaranteed to generate a reset.
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be con-
nected to VCC through a low-pass filter.
This is the analog reference pin for the A/D Converter.
6 ATmega165/V
2573AS–AVR–06/04

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