ATA6663 Ver la hoja de datos (PDF) - Atmel Corporation
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ATA6663 Datasheet PDF : 20 Pages
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Atmel ATA6663/ATA6664
6. Electrical Characteristics (Continued)
5V < VS < 27V, Tj = –40°C to +150°C
No. Parameters
Test Conditions
Pin Symbol Min. Typ. Max.
Leakage current at loss of
7.12
battery; node has to substain the VBAT disconnected
current that can flow under this VSUP_Device = GND
condition; bus must remain
0V < VBUS < 18V
operational under this condition
6
IBUS_NO_Bat
0.1
2
7.13 Capacitance on pin LIN to GND
8 LIN Bus Receiver
6
CLIN
20
8.1 Center of receiver threshold
8.2 Receiver dominant state
8.3 Receiver recessive state
8.4 Receiver input hysteresis
8.5
Pre-wake detection LIN
High-level input voltage
VBUS_CNT =
(Vth_dom + Vth_rec) / 2
VEN = 5V
VEN = 5V
VHYS = Vth_rec – Vth_dom
6
VBUS_CNT
0.475 ×
VS
0.5 ×
VS
0.525
× VS
6
VBUSdom
–27
0.4 ×
VS
6
VBUSrec
0.6 ×
VS
40
6
VBUShys
0.028 × 0.1 × 0.175
VS
VS × VS
6
VLINH
VS –
2V
VS +
0.3V
8.6
Pre-wake detection LIN
Low-level input voltage
Switches the LIN receiver on 6
VLINL
–27V
VS –
3.3V
8.7 LIN Pre-wake pull-up current
9 Internal Timers
VS < 27V
VLIN = 0V
6
ILINWAKE
–30 –10
9.1
Dominant time for wake-up via
LIN bus
VLIN = 0V
6
tBUS
30
90 150
9.2
Time of low pulse for wake-up
via pin WAKE
VWAKE = 0V
3
tWAKE
7
35
50
Time delay for mode change
9.3 from fail-safe mode to normal
mode via pin EN
VEN = 5V
2
tnorm
2
7
15
Time delay for mode change
9.4 from normal mode into sleep
mode via pin EN
VEN = 0V
2
tsleep
7
15
24
9.5
Atmel ATA6663:
TXD dominant time out time
VTXD = 0V
4
tdom
40
60
85
9.6
Power-up delay between VS = 5V
until INH switches to high
VVS = 5V
7, 8
tVS
200
9.7
Monitoring time for wake-up via
LIN bus
6
tmon
6
10
15
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Unit Type*
µA A
pF D
V
A
V
A
V
A
V
A
V
A
V
A
µA A
µs
A
µs
A
µs
A
µs
A
ms A
µs
A
ms A
13
9146D–AUTO–09/10
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