4.2 Overview
The ATA6602/ATA6603 uses a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATA6602/ATA6603 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
4.2.1 Block Diagram
Figure 4-1. Block Diagram
GND
VCC
Watchdog
Timer
Watchdog
Oscillator
Oscillator Circuits /
Clock Generation
EEPROM
8 bit T/C 0
8 bit T/C 2
Power Supervision
POR / BOD and
Reset
Flash
debugWIRE
Program
Logic
SRAM
AVR CPU
16 bit T/C 1
2
A/D Converter
AVCC
AREF
GND
Analog
Compensation
Internal
6
Bandgap
USART 0
SPI
TWI
Port D (8)
PD[0..7]
Port B (8)
PB[0..7]
Port C (7)
PC[0..6]
RESET
ADC[6..7]
XTAL[1..2]
26 ATA6602/ATA6603
4921C–AUTO–01/07