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AT90S1200 Ver la hoja de datos (PDF) - Atmel Corporation

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AT90S1200 Datasheet PDF : 71 Pages
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Table 6. Watchdog Timer Prescale Select
WDP2
0
WDP1
0
WDP0
0
Number of WDT
Oscillator Cycles
16K cycles
Typical Time-out
at VCC = 3.0V
47 ms
Typical Time-out
at VCC = 5.0V
15 ms
0
0
1
32K cycles
94 ms
30 ms
0
1
0
64K cycles
0.19 s
60 ms
0
1
1
128K cycles
0.38 s
0.12 s
1
0
0
256K cycles
0.75 s
0,24 s
1
0
1
512K cycles
1.5 s
0.49 s
1
1
0
1,024K cycles
3.0 s
0.97 s
1
Note:
1
1
2,048K cycles
6.0 s
1.9 s
The frequency of the Watchdog Oscillator is voltage dependent as shown in Typical
Characteristicson page 51.
The WDR (Watchdog Reset) instruction should always be executed before the Watchdog
Timer is enabled. This ensures that the reset period will be in accordance with the
Watchdog Timer prescale settings. If the Watchdog Timer is enabled without Reset, the
Watchdog Timer may not start to count from zero.
To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset
before changing the Watchdog Timer Prescale Select.
24 AT90S1200
0838HAVR03/02

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