AT89C51RB2/RC2
Table 16. CKCON1 Register
CKCON1 - Clock Control Register (AFh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
SPIX2
Bit
Number
7
6
5
4
3
2
1
0
Bit
Mnemonic Description
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
SPIX2
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reset Value = XXXX XXX0b
Not bit addressable
19
4180E–8051–10/06