AT49BV802DT Ver la hoja de datos (PDF) - Atmel Corporation

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AT49BV802DT

8-megabit (512K x 16/1M x 8) 3-volt Only Flash Memory

Atmel Corporation 

3. Block Diagram

I/O0 - I/O15/A-1

OUTPUT

BUFFER

INPUT

BUFFER

A0 - A18

INPUT

BUFFER

ADDRESS

LATCH

Y-DECODER

X-DECODER

IDENTIFIER

REGISTER

STATUS

REGISTER

DATA

COMPARATOR

Y-GATING

MAIN

MEMORY

COMMAND

REGISTER

WRITE STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

CE

WE

OE

RESET

BYTE

RDY/BUSY

VCC

GND

4. Device Operation

4.1 Read

The AT49BV802D(T) is accessed like an EPROM. When CE and OE are low and WE is high,

the data stored at the memory location determined by the address pins are asserted on the out-

puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus contention.

4.2 Command Sequences

When the device is first powered on, it will be reset to the read or standby mode, depending

upon the state of the control line inputs. In order to perform other device functions, a series of

command sequences are entered into the device. The command sequences are shown in the

“Command Definition Table” on page 13 (I/O8 - I/O15 are don’t care inputs for the command

codes). The command sequences are written by applying a low pulse on the WE or CE input

with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE

or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard

microprocessor write timings are used. The address locations used in the command sequences

are not affected by entering the command sequences.

4 AT49BV802D(T)

3626A–FLASH–2/07

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