AT49BV802AT Ver la hoja de datos (PDF) - Atmel Corporation
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Fabricante
AT49BV802AT Datasheet PDF : 29 Pages
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Block Diagram
AT49BV802A(T)
I/O0 - I/O15/A-1
OUTPUT
BUFFER
INPUT
BUFFER
A0 - A18
INPUT
BUFFER
ADDRESS
LATCH
Y-DECODER
X-DECODER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
Y-GATING
MAIN
MEMORY
COMMAND
REGISTER
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
BYTE
RDY/BUSY
VCC
GND
Device
Operation
READ: The AT49BV802A(T) is accessed like an EPROM. When CE and OE are low and WE
is high, the data stored at the memory location determined by the address pins are asserted
on the outputs. The outputs are put in the high impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the “Command Definition in Hex” table on page 11 (I/O8 - I/O15 are
don’t care inputs for the command codes). The command sequences are written by applying a
low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address
is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the
first rising edge of CE or WE. Standard microprocessor write timings are used. The address
locations used in the command sequences are not affected by entering the command
sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs.
ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-
mand or individual sectors can be erased by using the Sector Erase command.
3
3405C–FLASH–9/04
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