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AT48802-16QC

Spread-Spectrum Signal Processor Integrated Circuit

Atmel Corporation 

AT48802

Frequency Diversity Improves

Signal-to-Noise Ratio

Built into the AT48802 is an exclusive frequency diversity

function, which enhances protection from PN noise due to

imperfect correlation. The chip encodes the PN code se-

quence such that when spread, the information is modu-

lated and transmitted redundantly in two side lobes. That

is, the redundant information is contained in two main

lobes with a null at the carrier instead of the classical sin-

gle lobe spreading spectra. The spreading bandwidth also

doubles, effectively doubling the spreading chip rate. This

has the benefit of increased processing gain and greatly

reducing the residual PN noise near the carrier after cor-

relation. The frequency diversity can be user enabled by

setting the BW (Band-Width) bit high in the PN register

(Register 2, bit 7 for Receive PN, and Register 4, bit 7 for

Transmit PN). The transmit and receive PN generators are

set independently.

Chip Phase and Tau-Dither Control

The chip phase control circuit enables the user to step the

chip phase in either direction by amounts from 1/16 to 8/16

chip per update. The size of the step is set in R5 b0-2, the

step direction is controlled by the ADVANCE line, and the

command to do a step is by pulsing the UPDATE line. The

maximum allowed update rate is MCLOCK/32.

The tau-dither circuit is used to assist in the tracking a cor-

relation peak. This is done as follows. When the locally

generated receive PN is a good match to the incoming sig-

nal at RF, then the RF signal is accurately despread and

the signal energy is gathered into a narrow spectral region

around the carrier. If a narrow IF filter is used to filter this

signal, then when the chip phase match to the incoming

signal is good then the most possible power will get

through the narrow IF filter; when the chip phase is ad-

vanced or retarded from the best place, then the signal

power in a narrow band will fall. The tau-dither circuits,

when activated, step the PN chip phase back and forth by

a settable amount at a rate of TDD/2. If one looks at the

RF module RSSI (receive signal strength indicator) by us-

ing the A/D converter interface, then when the PN phase

is, on the average, optimum then the alternating output of

RSSI will show small variation at a rate of TDD/2. If the

peak is not centered, then the RSSI variation at TDD/2

measured through the A/D converter interface, will be-

come larger because one phase of tau-dither will produce

less RSSI than the other. Now one can track the peak by

using the microprocessor to close this control loop which

has as an input to the RSSI variation at TDD/2 measured

through the A/D converter interface and has output using

the UPDATE and ADVANCE controls. The control loop

should null the TDD/2 signal.

The available tau-dither amounts are 1/16 chip peak-to-

peak, to 15/16 chip peak-to-peak, set at R5 b3-5. Dither

on/off is controlled via R0 b4 (track = high = dither on ).

The tau-dither phase is actually only a retard or no retard

with respect to the chip phase when tau-dither is off, this

is a detail which the control system designer may need.

If the tau-dither amplitude is changed it will not take affect

until the receive PN code is reloaded. The DITHER output

of the chip tells the microprocessor whether the dither

phase is retarded (High) or not retarded. High is retarded.

RSSI Interface

The purpose of this circuitry is to provide an interface to a

serial A/D converter and an integrate/dump filter, if de-

sired. The interface is synchronized to TDD. The data from

the A/D converter is converted to parallel and loaded to

the register at R8 b0-7. The RSSI function provides an in-

tegrated/dump command output with timing completely

adjustable throughout the TDD cycle and also completely

adjustable for pulse width, except the hardware will not al-

low the timing of RSSI ID to conflict with the A/D converter

command. This allows optimum filtering of the RSSI signal

if desired. The adjustable timing is necessary to allow for

different RF designs with different amounts of delay in the

IF filter. The sense of the RSSI ID output, that is, which

way is integrate and which way is dump, is controlled via

RC b6-7

RSSI ID timing is set via RC b0-5 for delay and RD b0-5

for pulse width. The smallest step is MCLK/32 = 2 us for a

15.36 MHz clock. The 5 bits allow adjustment over a range

of TDD/2. In order to get the other half TDD cycle, one

must invert the RSSI ID bits at RC b6-7, which will invert

the waveform.

Figure 3 shows the A/D converter timing for a converter

such as the Linear Technology LTC 1196 National Semi-

conductor ADC0831 or similar.

2-7

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