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NX25F641C-3T

64M-BIT SERIAL FLASH MEMORY WITH 4-PIN SPI INTERFACE

NexFlash -> Winbond Electronics 

NX25F641C

SERIAL FLASH SECTOR AND SRAM READ

COMMANDS

Transfer Sector to SRAM (53H and 56H)

The Transfer Sector to SRAM command transfers the con-

tents of a specified 528-byte sector directly to the SRAM.

Writing to a sector is accomplished by first bringing CS

low and shifting in the Transfer Sector to SRAM com-

mand (53H and 5DH) followed by a 16-bit

“sector-address” field. Although the sector-address field

is 16-bits, only bits S[13:0] are used. The uppermost

sector address bits are not used but must be clocked

in (use 0 data). Following the sector address, a 32-bit

“0” field is clocked into the device. The transfer opera-

tion will start and the Busy and TR bit in the status

register will be set.

Read SRAM (71H and 73H)

The Read SRAM command (71H and 73H) provides

access to the 528-byte SRAM independent of any Flash

memory array operations. The TR bit in the status register

should be checked first if Transfer Sector to SRAM or

Refresh Sector commands are used. Reading from the

SRAM is accomplished by first bringing CS low then shift-

ing in the Read SRAM command (71H or 73H) followed

by its 16-bit “byte-address” field is clocked into the device

to designate the starting location within the 528-byte sec-

tor. Only B[9:0] of the byte-address field are used; the

uppermost bits are not used but must be clocked in (use 0

for data). Only byte-addresses of 0 to 209H (528 bytes)

are valid. Following the byte-address field, 8 control clocks

are required with data=0. The Serial Data

Output (SO) will change from a high-impedance state and

begin to drive the output. If SO uses the rising edge of

clock (configuration register RCE=1), the output will be

driven after the last control clock. If SO uses the falling

edge of clock (RCE=0), the output will be driven on the

next falling edge of clock. The data field is shifted out with

the least significant byte first (i.e., byte-00H, byte-01H,

...). The bit order within each byte is the most significant

bit first (i.e.,D7,...D0). The byte-address is internally

incremented to the next higher byte address as the clock

continues.

Write Disable (04H)

The Write Disable command (04H) protects the Flash

memory array from being programmed. Once issued,

further Write to Sector or Transfer SRAM to Sector com-

mands will be ignored. The status of the write protect state

can be read in the status register. The Write Disable com-

mand sequence is completed by asserting CS high after

eight additional clocks.

Write to Sector Using SRAM (F3H or 94H)

Before writing to a sector in the Flash memory array,

all hardware and software write protection must be in

an enabled state. This means that the WP pin must be

in a high state, a Write Enable command must have

previously been issued, and the sector location that is

to be written to must be outside the write protect range

set in the configuration register. Additionally, the Ready/

Busy status should be checked to confirm that the

memory array is available to be written to, refer to fig-

ures 8 and 12 for block diagram.

Writing to a sector is accomplished by first bringing CS

low and shifting in the Write to Sector Using SRAM com-

mand (F6H or 98H) followed by a 16-bit “sector-address”

field. Although the sector-address field is 16-bits, only

bits S[13:0] are used. The uppermost sector address

bits are not used but must be clocked in (use 0 data).

Following the sector address, a 16-bit “byte-address”

field is clocked into the device to designate the starting

location within the 528-byte sector. Only bits B[9:0] of

the byte-address field are used and only values of

0-209H (528 bytes) are valid.

After the byte-address has been loaded, data is shifted

into the 528-byte SRAM, which serves as a temporary

storage buffer. Existing data in the SRAM will be

written over. The byte order of the data shifted into the

SRAM is least significant byte first (i.e., byte-00H,

byte-01H,...). The bit order within each byte is most sig-

nificant bit first (i.e., D7,...D0). The byte-address is

automatically incremented to the next higher byte ad-

dress as the clock continues. When the last byte ad-

dress to be written is reached, the command can be

completed with an additional eight control clocks (with

data=0) followed by asserting CS high.

16

NexFlash Technologies, Inc.

PRELIMINARY NXSF032A-0502

05/06/02 ©

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