ASC7621 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

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Fabricante

ASC7621

HARDWARE MONITOR WITH INTEGRATED FAN CONTROL

Unspecified 

aSC7621

Register 6D-6Eh: Thermal Zone Hysteresis

Register Read/

Address Write

Register

Name

Bit 7 Bit 6

(MSB)

Zone 1 and

6Dh

R/W Zone 2

H1-3 H1-2

Hysteresis

Zone 3 and

6Eh

R/W Zone 4

H3-3 H3-2

Hysteresis

Bit 5

H1-1

H3-1

Bit 4

H1-0

H3-0

Bit 3

H2-3

H4-3

Bit 2

H2-2

H4-2

Bit 1 Bit 0 Default Lock

(LSB) Value

H2-1 H2-0

44

X

H4-1 H4-0

44

X

If the temperature is above Fan Temp Limit, then drops below Fan Temp Limit, the following will occur:

• The fan will remain on, at Fan PWM Minimum, until the temperature goes a certain amount below Fan Temp Limit.

• The Hysteresis registers control this amount. See below table for details, all values from 0°C to 15°C are possible.

This register becomes read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to

these registers shall have no effect.

Temperature

Zone Hysteresis Hn-[3:0]

0°C

1°C

4°C (default)

10°C

15°C

0000

0001

0100

1010

1111

Table 28 Zone Hysteresis Register Format

Register 75h: Fan Spin-Up Mode

Register Read/ Register Bit 7

Address Write Name (MSB)

75h

R/W

Fan Spin- Tach4

Up Mode Disable

Bit 6

Tach3/4

Disable

Bit 5

Tach2

Disable

Bit 4

Tach1

Disable

Bit 3

RES

Bit 2

PWM3

SU

Bit 1

PWM2

SU

Bit 0 Default Lock

(LSB) Value

PWM1

SU

00

X

The PWM SU bit configures the PWM spin-up mode. If PWM SU is cleared the spin-up time will terminate after time

programmed by the Fan Configuration register has elapsed. When set to 1, the spin-up time will terminate early if the TACH

reading interpreted as RPM exceeds the Tach Minimum RPM value or after the time programmed by the Fan Configuration

register has elapsed, which ever occurs first. Note that the magnitudes of the tach readings and the limits in the registers

represent a time period that is inversely proportional to RPM.

This register becomes Read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write

to this register shall have no effect.

© Andigilog, Inc. 2006

- 41 -

www.andigilog.com

October 2006 - 70A06010

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