AS7C1028 Ver la hoja de datos (PDF) - Alliance Semiconductor
Número de pieza
componentes Descripción
Fabricante
AS7C1028 Datasheet PDF : 8 Pages
| |||
AS7C1028
®
Functional description
The AS7C1028 is a 5V high-performance CMOS 1,048,576-bit Static Random-Access Memory (SRAM) device organized
as 262,144 words × 4 bits. It is designed for memory applications requiring fast data access at low voltage, including
PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V
operation without sacrificing performance or operating margins.
The device enters standby mode when CE is high. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output
enable access times (tOE) of 6 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory
expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C1028 is packaged in
high volume industry standard packages.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.5
+7.0
V
Voltage on any pin relative to GND
Vt2
–0.5
VCC + 0.5
V
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC applied
PD
–
Tstg
–55
Tbias
–55
1.25
W
+125
oC
+125
oC
DC current into outputs (low)
IOUT
–
50
mA
Note:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
H
X
X
L
H
H
L
H
L
L
L
X
Notes:
H = VIH, L = VIL, x = Don’t care.
VLC = 0.2V, VHC = VCC - 0.2V.
Other inputs ≥ VHC or VLC.
Data
High Z
High Z
DOUT
DIN
Mode
Standby (ISB, ISB1)
Output disable (ICC)
Read (ICC)
Write (ICC)
12/5/06; V.1.0
Alliance Memory
P. 2 of 8
Share Link: 