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AS1536-BSOT

12-Bit, Single Supply, Low-Power, 73ksps A/D Converters

austriamicrosystems AG 

AS1536/AS1537

Datasheet - Application Information

9 Application Information

Initialization

When power is first applied, and if SHDNN is not pulled low, it takes the fully discharged 4.7µF reference bypass

capacitor up to 20ms to provide adequate charge for specified accuracy.

With an external reference, the initialization time is 10µs after the power supplies have stabilized.

Note: A/D conversions must not be started during initialization of the AS1536/AS1537.

Serial Interface

The AS1536/AS1537 fully support SPI, QSPI, and Microwire interfaces. For SPI, select the correct clock polarity and

sampling edge in the SPI control registers (set CPOL = 0 and CPHA = 0).

Microwire, SPI, and QSPI all transmit a byte and receive a byte at the same time.

Serial Interface Configuration

The AS1536/AS1537 serial interface can be configured with the following procedure:

1. Put the microprocessor’s serial interface into master mode (so that it generates the serial clock).

2. Select a clock frequency up to 2.1MHz.

3. Keeping SCLK low, pull CSN low via one of the microprocessor’s general-purpose I/O lines.

4. Monitor DOUT for its rising edge to determine the EOC, or wait the maximum conversion time specified before acti-

vating SCLK.

5. Activate SCLK for a minimum of 11 clock cycles. The first falling clock edge produces the MSB of the conversion.

Output data transitions on the falling edge of SCLK, and is available in MSB-first format at pin DOUT. Observe the

SCLK to DOUT valid timing characteristic. Data can be clocked into the microprocessor on the rising edge of SCLK.

6. CSN should be pulled high at or after the 13th falling clock edge. If CSN remains low, trailing zeros are clocked out

after the LSB.

7. With CSN = high, wait the minimum specified time, tCS, before initiating a new conversion by pulling CSN low. If a

conversion is aborted by pulling CSN high before the conversion’s end, wait for the minimum acquisition time, tACQ,

before starting a new conversion.

Note: CSN must be held low until all data bits are clocked out.

8. Data can be output in two bytes or continuously (see Figure 34 on page 18). The bytes contain the result of the con-

version padded with one leading 1, two sub-bits, and trailing 0s.

SPI and Microwire Interfaces

When interfacing the AS1536/AS1537 to a microprocessor’s SPI or Microwire interface (see Figure 32 and Figure 33),

set SPI control registers CPOL = 0 and CPHA = 0.

Figure 32. SPI Serial Interface Connections

SCK

SSM

CPU

I/O

MISO

8

SCLK

7 AS1536/

CSN AS1537

6

DOUT

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