AS1536-BSOT Ver la hoja de datos (PDF) - austriamicrosystems AG

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AS1536-BSOT

12-Bit, Single Supply, Low-Power, 73ksps A/D Converters

austriamicrosystems AG 

AS1536/AS1537

Datasheet - Detailed Description

9. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CSN,

produce trailing zeros at DOUT and have no effect on the conversion process.

10. For minimum cycle time, clock out the data with 12.5 clock cycles at full speed using the rising edge of DOUT as

the EOC signal. Pull CSN high after reading the conversion’s LSB. After the specified minimum time (tCS) CSN can

be pulled low to initiate the next conversion.

Figure 25. Serial Interface Standard Cycle Timing Diagram

CSN

SCLK

DOUT

Interface Idle

Track/Hold

Stage

Track

Cycle Time

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Conversion EOC

In Progress

Clock Out Serial Data

Trailing

0s

Idle

Hold

tCONV

7.5µs

0µs

Track

12.5 x 0.476µs = 5.95µs

Total = 13.7µs

0µs

tCS

0.24µs

Hold

Figure 26. Serial Interface Minimum Cycle Timing Diagram

CSN

SCLK

DOUT

Interface

Idle

Track/Hold

Stage

Track

Cycle Time

Conversion

In Progress

Hold

tCONV

7.5µs

EOC

0µs

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Clock Out Serial Data

Track

12.5 x 0.476µs = 5.95µs

Total = 13.7µs

Idle

tCS

0.24µs

Figure 27. Detailed Serial Interface Timing Diagram

CSN

tCSO

SCLK

tDO

DOUT

tDV

tCONV

Internal

Track/Acquire

Track/Hold

Hold

tAP

tSTR

tCS

tCH

tCL

B2

B1

tTR

B0

Track/Acquire

Hold

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