AS1332 Ver la hoja de datos (PDF) - austriamicrosystems AG
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AS1332 Datasheet PDF : 20 Pages
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AS1332
Datasheet - Detailed Description
Figure 31. Typical Operating System Circuit
VIN
2.7V to 5.5V
C1
PVIN
VDD
10 µF
L1
VOUT
lid System
va Controller
DAC
ON/OFF
AS1332
3.3 µH
SW
FB
1.3V to 3.16V
VOUT = 2.5 x VCON
C2
4.7 µF
AGND PGND
G till Operating the AS1332
s AS1332’s control block turns on the internal PFET (P-channel MOSFET) switch during the first part of each switching
cycle, thus allowing current to flow from the input through the inductor to the output filter capacitor and load. The
A t inductor limits the current to a ramp with a slope of around (VIN - VOUT) / L, by storing energy in a magnetic field.
s n During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and
then turns the NFET (N-channel MOSFET) synchronous rectifier on. As a result, the inductor’s magnetic field
e collapses, generating a voltage that forces current from ground through the synchronous rectifier to the output filter
m t capacitor and load.
While the stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope
a n around VOUT / L. The output filter capacitor stores charge when the inductor current is high, and releases it when low,
smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to
o control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave
formed by the switch and synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter
c capacitor.
The output voltage is equal to the average voltage at the SW pin.
l While in operation, the output voltage is regulated by switching at a constant frequency and then modulating the
energy per cycle to control power to the load. Energy per cycle is set by modulating the PFET switch on-time pulse
a width to control the peak inductor current. This is done by comparing the signal from the current-sense amplifier with a
slope compensated error signal from the voltage-feedback error amplifier. At the beginning of each cycle, the clock
ic turns on the PFET switch, causing the inductor current to ramp up. When the current sense signal ramps past the error
amplifier signal, the PWM comparator turns off the PFET switch and turns on the NFET synchronous rectifier, ending
the first part of the cycle.
n If an increase in load pulls the output down, the error amplifier output increases, which allows the inductor current to
ramp higher before the comparator turns off the PFET. This increases the average current sent to the output and
h adjusts for the increase in the load. Before appearing at the PWM comparator, a slope compensation ramp from the
c oscillator is subtracted from the error signal for stability of the current feedback loop. The minimum on time of PFET in
Te PWM mode is 50ns (typ.)
www.austriamicrosystems.com/DC-DC_Step-Down/AS1332
Revision 1.02
12 - 19
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