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APW7079-50DI-TRG Ver la hoja de datos (PDF) - Anpec Electronics

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APW7079-50DI-TRG Datasheet PDF : 15 Pages
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APW7079
Pin Description
PIN
NO.
NAME
FUNCTION
Junction of N-FET and P-FET Drains. Connect the inductor here and minimize the trace area for
1
LX
lowest EMI.
2
VOUT
Converter output and control circuitry bias supply pin.
3
GND
Ground.
Block Diagram
VOUT
2
0.9µs Min.
off-time
Error
Comparator
-
+
VREF
Thermal
Shutdown
Control
Logic
Zero Crossing
Comparator
+
-
Gate
Driver
Synchronous
Switch
3 LX
Main Switch
4µs Max.
on-time
Typical Application Circuit
Current Limit
Comparator
+
-
Soft
start
RSENSE
1
GND
VIN IIN
L1
APW7079
IOUT
22µH
LX
VOUT
C1
22µF
GND
Copyright © ANPEC Electronics Corp.
7
Rev. A.3 - Oct., 2008
www.anpec.com.tw

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