APW7062B(2008) Ver la hoja de datos (PDF) - Anpec Electronics
Número de pieza
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Fabricante
APW7062B Datasheet PDF : 18 Pages
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APW7062B
Application Information (Cont.)
Compensation (Cont.)
The closed loop gain of the converter can be written as:
R2
GAINLC x GAINPWM x R1+ R2 x GAINAMP
Figure 6 shows the converter gain and the following guide-
lines will help to design the compensation network.
1.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) x FS >FO>FZ
Use the following equation to calculate R3:
R3 = ∆VOSC × FESR × R1 + R2 × FO
VIN
FLC 2
R2
gm
Where:
gm=900µA/V
2.Place the zero FZ before the LC filter double poles FLC:
F = 0.75 x F
Z
LC
Calculate the C1 by the equation:
C1
=
2×
1
π ×R1× FLC × 0.75
3. Set the pole at the half the switching frequency:
FP = 0.5xFS
Calculate the C2 by the equation:
C2
=
C1
π×R3 × C1×FS −1
FZ=0.75FLC
20⋅log(gm⋅R3)
FP=0.5FS
Compensation
Gain
FLC
VIN
20 ⋅ log
? VOSC
FESR
PWM &
Filter Gain
FO
Converter
Gain
Frequency
Figure 6. Converter Gain & Frequency
MOSFET Selection
The selection of the N-channel power MOSFETs are de-
termined by the RDS(ON), reverse transfer capacitance (CRSS)
and maximum output current requirement.The losses in
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
losses are approximately given by the following :
PUPPER
=
I2
out
(1+
TC)(RDS(ON))D
+
(0.5)(Iout)(VIN)(tsw)FS
PLOWER = Iout2(1+ TC)(RDS(ON))(1-D)
where I is the load current
OUT
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tsw is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction losses while
the upper MOSFET include an additional transition loss.
The switching internal, t , is the function of the reverse
sw
transfer capacitance CRSS. Figure 7 illustrates the switch-
ing waveform internal of the MOSFET.
The (1+TC) term is to factor in the temperature depen-
dency of the R and can be extracted from the “R
DS(ON)
DS(ON)
vs Temperature” curve of the power MOSFET.
Layout Consideration
In high power switching regulator, a correct layout is im-
portant to ensure proper operation of the regulator. In
general, interconnecting impedances should be mini-
mized by using short and wide printed circuit traces. Sig-
nal and power grounds are to be kept separate and finally
combined using ground plane construction or single point
grounding. Figure 8 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
lines should be placed close together. Below is a check-
list for your layout:
• Keep the switching nodes (UGATE, LGATE, and
PHASE) away from sensitive small signal nodes since
these nodes are fast moving signals. There fore keep
traces to these nodes as short as possible.
•
The ground return of C must return to the combine
IN
COUT (-) terminal.
• Capacitor CBOOT should be connected as close to the
BOOT and PHASE pins as possible.
Copyright © ANPEC Electronics Corp.
13
Rev. A.4 - Oct., 2008
www.anpec.com.tw
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