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APT7843 Ver la hoja de datos (PDF) - Anpec Electronics

Número de pieza
componentes Descripción
Fabricante
APT7843
Anpec
Anpec Electronics Anpec
APT7843 Datasheet PDF : 18 Pages
First Prev 11 12 13 14 15 16 17 18
APT7843
CS
DCLK
DIN
BUSY
DOUT
1
8
1
S
CONTROL BITS
8
1
8
1
S
CONTROL BITS
11 10 9 8 7 6 5
43210
11 10 9
FIGURE 6. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required
with Dedicated Serial Port.
16-Clocks or 15-Clocks per Con-
version
The APT7843 will alow a conversion every 16 clock
cycles, as shown in Figure 6. This figure shows
possible serial communication occurring with other
serial peripherals between each byte transfer between
the processor and the converter.
Figure 7 provides the fastest way to clock the
APT7843. This method will not work with the serial
interface of most microcontrollers and digital signal
processors as they are generally not capable of pro-
viding 15 clock cycles per serial transfer. However,
this method could be used with field programmable
gate arrays (FPGAs) or application specific integrated
circuits (ASICs). (Note that this effectively increases
the maximum conversion rate of the converter).
AC Timing
Figure 8 and Table VI provide detailed timing of the
APT7843. Table VII provide detailed timing of low power
VCC=2.4V.
Copyright ANPEC Electronics Corp.
11
Rev. A.8 - Apr., 2002
www.anpec.com.tw

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