MR27V3266D Ver la hoja de datos (PDF) - Oki Electric Industry

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MR27V3266D

2M x16 / 1M x32 Synchronous OTP ROM

Oki Electric Industry 

1 Semiconductor

Clock Suspend @ CAS Latency = 5, Burst Length = 4

MR27V3266D

CLK

012

345

6 7 8 9 10 11 12 13 14 15 16 17 18 19

CKE

tCC

tCH tCL

tCKE tCKE

tCKE

tCKE

CS

RAS

CAS

ADDR

DQ

tSI

tHI

tRCD

Ra

Ca

tCCD

Cb

Read "a" operation ( Note2 )

a0

a1

a2

( Note1 )

Read "b" operation

a3 b0 b1 b2 b3

MR

Row Active Read

Read Exit

Exit

Clock Suspend

Clock Suspend

Entry

Entry

Don't Care

Note

1. At cycle number 9, 12, 13, rising edge of internal clock is omitted because of low level CKE at cycle 8, 11,12.

2. Clock suspend is defined with the low level CKE sampled in the period of Read operation.

August , 1999

Revision 2.4

32M Synchronous OTP

20

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