AN726 Ver la hoja de datos (PDF) - Silicon Laboratories

Número de pieza

componentes Descripción

Fabricante

AN726

UTILITY CLASS-D TOOLSTICK USER’S GUIDE

Silicon Laboratories 

AN726

5.5. Stereo Jack Input Mode

In stereo jack input mode, the goal is to sample at an even division of the EPCA0 update frequency to provide the

lowest distortion attainable. The data from the ADCs is 12-bit unsigned.

Class-D RD Board

R

SiM3U1xx

SARADC0

SARADC1

EPCA

L

Figure 10. Stereo Jack Input Mode Block Diagram

This mode measures the input source from the stereo jack (J1) using both SARADC modules, performs the EWMA

algorithm, quantizes the data to 9 bits, and outputs the PWM waveform on the EPCA0 module. Figure 11 shows

the data flow for the stereo input jack mode.

The Class-D ToolStick board automatically biases the input waveform to VREF/2. On hardware that does not do

this, an additional dc offset adjustment algorithm may be required.

R

hardware

gain stage

hardware

gain stage

SARADC0

SARADC1

SiM3U1xx

adjusting

DC offset

algorithm

remainder-

weighted

dither

EPCA

EWMA

9-bit

quantization

L

Figure 11. Stereo Jack Input Mode Flow Diagram

12

Rev. 0.1

Share Link: