AL701 Ver la hoja de datos (PDF) - AverLogic Technologies Inc

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AL701

QUAD Video Processor

AverLogic Technologies Inc 

AL700/701/710

7.10 Image Data Upload

AL700/701/710 supports 8-bit host bus that allows the microprocessor to directly read the

digital image data from the SDRAM video memory. UPIMGCTR (#58h) register controls

the image data uploading attributes. UPIMGYDP (#59h) and UPIMGCDP (#5Ah) registers

store the Luminance and Chrominance data of a pixel, respectively.

Internal image read counter will automatically increase when read UpImgYDP or

UPImagCDP. To ensure image uploading correctly, the monitor output must be set to freeze

mode and the internal image read counter must be reset before uploading an image.

The pixel number of an image depends on the monitor display output mode. The first pixel

is the upper most, top left point of a picture image. The image data is sequentially stored in

the memory. The first pixel data of the following horizontal line is next to the last pixel data

of the previous horizontal line. The microprocessor should calculate the image resolution,

such as vertical and horizontal total pixels, to the read-out data so that it can re-build the

picture image properly.

7.11 Interrupt

AL700/701/710 interrupt function is supported by INTR pin, INTRSTATUS (#06h) and

INTRMASK (#07h) registers. The Intr_pol (#03h <4>) controls the polarity of INTR pin.

The INTR pin is active High if Intr_pol is set to 1 and vice versa. INTRSTATUS reflects

the interrupt status of video loss or motion detection. Each bit of INTRSTATUS indicates

one interrupt event and is active High. Set ‘1’ to the corresponding bit in the INTRSTATUS

register will clear the interrupt status.

Each interrupt status bit has its mask bit to disable the hardware INTR signal. Set ‘1’ to the

corresponding bit in the INTRMASK register will prohibit that channel to activate the

interrupt. The mask bit affects only the action of INTR and will not change the interrupt

status in INTRSTATUS register. AL700/701/710 will issue an “INTR” request to an

external micro-controller if there is at least one non-zero bit in the INTRSTATUS register

and its corresponding mask bit is 0.

06h

INTRSTATUS

R/W

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

MotionD MotionC MotionB MotionA VdoLossD VdoLossC VdoLossB VdoLossA

07h

INTRMASK

R/W

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mask_MD Mask_MC Mask_MB Mask_MA Mask_VLD Mask_VLC Mask_VLB Mask_VLA

If INTR is active High, then using Boolean logic equation to express INTR is as follows:

INTR = (MotionD AND Mask_MD) OR (MotionC AND Mask_MC) OR (MotionB AND

Mask_MC) OR (MotionA AND Mask_MA) OR (VdoLossD AND Mask_VLD)

OR (VdoLossC AND Mask_VLC) OR (VdoLossB AND Mask_VLB) OR

(VdoLossA AND Mask_VLA)

©2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 28

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