Downconverter Main and Reference Divider Registers
AIT1042
The downconverter main and reference divider registers are used to set the A, B and R counters in the
downconverter synthesizer. The output frequency for the synthesizer is computed using the following
equation:
fosc
=
[(64)(B) +
R
A]
fxtal
where:
fOSC is the downconverter local oscillator (LO2) frequency
B is the divide ratio of the B counter (2 to 2047 inclusive)
A is the divide ratio of the A counter (0 < A < P-1, A < B)
fXTAL is the frequency of the reference crystal oscillator
R is the divide ratio of the R counter (2 to 4095 inclusive)
The preset modulus of the prescalar is 64 and is not programmable.
In the main divider register, the A counter is set via Bits 2-8 and the B counter is set with Bits 9-19. In the
reference divider register, the R counter is set with Bits 2-13. The remaining bits must use the fixed values
indicated in Tables 15 and 16.
MSB
Table 15: Downconverter Main Divider Register
PLL2_Main (Downconverter Main Divider Register)
First data byte
Second data byte
Third data byte
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
0000
B counter
A counter
LSB
10
01
MSB
Table 16: Downconverter Reference Divider Register
PLL2_Ref (Downconverter Reference Divider Register)
First data byte
Second data byte
Third data byte
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
000 100 1000
R counter
LSB
10
00
PRELIMINARY DATA SHEET - Rev 1.0
15
02/2009