ADSP-21261 Ver la hoja de datos (PDF) - Analog Devices
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ADSP-21261 Datasheet PDF : 48 Pages
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ADSP-21261/ADSP-21262/ADSP-21266
ADDRESS DATA PINS AS FLAGS
To use these pins as flags (FLAG15–0), set (= 1) Bit 20 of the
SYSCTL register and disable the parallel port.
Table 7. AD15–0 to FLAG Pin Mapping
AD Pin
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Flag Pin
FLAG8
FLAG9
FLAG10
FLAG11
FLAG12
FLAG13
FLAG14
FLAG15
AD Pin
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
Flag Pin
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
Boot Modes
Table 8. Boot Mode Selection
BOOT_CFG1–0
00
01
10
11
Booting Mode
SPI Slave Boot
SPI Master Boot
Parallel Port Boot via EPROM
Reserved
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
Table 9. Core Instruction Rate/CLKIN Ratio Selection
CLK_CFG1–0
00
01
10
11
Core to CLKIN Ratio
3:1
16:1
8:1
Reserved
ADDRESS DATA MODES
Table 10 shows the functionality of the AD pins for 8-bit and
16-bit transfers to the parallel port. For 8-bit data transfers, ALE
latches address bits A23–A8 when asserted, followed by address
bits A7–A0 and data bits D7–D0 when deasserted. For 16-bit
data transfers, ALE latches address bits A15–A0 when asserted,
followed by data bits D15–D0 when deasserted.
Table 10. Address/Data Mode Selection
EP Data
Mode
8-bit
8-bit
16-bit
16-bit
ALE
Asserted
Deasserted
Asserted
Deasserted
AD7–0
Function
A15–8
D7–0
A7–0
D7–0
AD15–8
Function
A23–16
A7–0
A15–8
D15–8
Rev. G | Page 13 of 48 | December 2012
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