ADSP-21161NKCA-100(RevA) Ver la hoja de datos (PDF) - Analog Devices
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ADSP-21161NKCA-100 Datasheet PDF : 60 Pages
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ADSP-21161N
Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew that
can be introduced in the transmission path between LDATA and
LCLK. Setup skew is the maximum delay that can be introduced
in LDATA relative to LCLK, (setup skew = tLCLKTWH min– tDLDCH
– tSLDCL). Hold skew is the maximum delay that can be introduced
in LCLK relative to LDATA, (hold skew = tLCLKTWL min – tHLDCH
– tHLDCL). Calculations made directly from speed specifications
will result in unrealistically small skew times because they include
multiple tester guardbands. The setup and hold skew times
shown below are calculated to include only one tester guardband.
ADSP-21161N Setup Skew = 1.5 ns max
ADSP-21161N Hold Skew = 1.5 ns max
Note that there is a two-cycle effect latency between the link port
enable instruction and the DSP enabling the link port.
Table 27. Link Ports – Receive
Parameter
Min
Max
Unit
Timing Requirements
tSLDCL
Data Setup Before LCLK Low
1
ns
tHLDCL
Data Hold After LCLK Low
3.5
ns
tLCLKIW
LCLK Period
tLCLK
ns
tLCLKRWL
LCLK Width Low
4.0
ns
tLCLKRWH
LCLK Width High
4.0
ns
Switching Characteristics
tDLALC
LACK Low Delay After LCLK High1
8
12
ns
1 LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver's link buffer is not about to fill.
RECEIVE
LCLK
LDAT7-0
LACK (OUT)
tLC LKRW H
tL CLK IW
tLCLKRWL
tSLDCL
IN
tHLDCL
tDLALC
Figure 30. Link Ports—Receive
REV. A
–41–
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