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ADN2819
(Rev.:RevC)

Multirate to 2.7 Gbps Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

Data Sheet

FUNCTIONAL DESCRIPTION

MULTIRATE CLOCK AND DATA RECOVERY

The ADN2819 will recover clock and data from serial bit

streams at OC-3, OC-12, OC-48, and GbE data rates as well as

the 15/14 FEC rates. The output of the 2.5 GHz VCO is divided

down in order to support the lower data rates. The data rate is

selected by the SEL[2..0] inputs (see Table 5).

Table 5. Data Rate Selection

SEL[2..0]

Rate

000

OC-48

001

GbE

010

OC-12

011

OC-3

100

OC-48 FEC

101

GbE FEC

110

OC-12 FEC

111

OC-3 FEC

Frequency (MHz)

2488.32

1250.00

622.08

155.52

2666.06

1339.29

666.51

166.63

LIMITING AMPLIFIER

The limiting amplifier has differential inputs (PIN/NIN) that are

internally terminated with 50 Ω to an on-chip voltage reference

(VREF = 0.6 V typically). These inputs are normally ac-coupled,

although dc-coupling is possible as long as the input common-

mode voltage remains above 0.4 V (see Figure 26, Figure 27, and

Figure 28 in the Applications Information section). Input offset

is factory trimmed to achieve better than 4 mV typical sensitivity

with minimal drift. The limiting amplifier can be driven

differentially or single-ended.

SLICE ADJUST

The quantizer slicing level can be offset by ±100 mV to mitigate

the effect of amplified spontaneous emission (ASE) noise by

applying a differential voltage input of ±0.8 V to SLICEP/N

inputs. If no adjustment of the slice level is needed, SLICEP/N

must be tied to VCC.

LOSS OF SIGNAL (LOS) DETECTOR

The receiver front end level signal detect circuit indicates when

the input signal level has fallen below a user adjustable threshold.

The threshold is set with a single external resistor from Pin 1,

THRADJ, to GND. The LOS comparator trip point versus the

resistor value is illustrated in Figure 4 (this is only valid for

SLICEP = SLICEN = VCC). If the input level to the ADN2819

drops below the programmed LOS threshold, SDOUT (Pin 45)

will indicate the loss of signal condition with a Logic 1. The

LOS response time is ~300 ns by design, but it is dominated by

the RC time constant in ac-coupled applications.

If using the LOS detector, the quantizer slice adjust pins must

both be tied to VCC. This is to avoid interaction with the LOS

threshold level.

ADN2819

Note that it is not expected to use both LOS and slice adjust at

the same time. Systems with optical amplifiers need the slice

adjust to evade ASE. However, a loss of signal in an optical link

that uses optical amplifiers causes the optical amplifier output

to be full-scale noise. Under this condition, the LOS would not

detect the failure. In this case, the loss of lock signal indicates

the failure because the CDR circuitry is unable to lock onto a

signal that is full-scale noise.

REFERENCE CLOCK

There are three options for providing the reference frequency to

the ADN2819: differential clock, single-ended clock, or crystal

oscillator. See Figure 17, Figure 18, and Figure 19 for example

configurations.

ADN2819

REFCLKP

BUFFER

REFCLKN

VCC

VCC

XO1

XO2

100kΩ 100kΩ

VCC/2

CRYSTAL

OSCILLATOR

VCC

REFSEL

Figure 17. Differential REFCLK Configuration

VCC

CLK

OSC OUT

REFCLKP

REFCLKN

NC

ADN2819

BUFFER

VCC

VCC

XO1

XO2

100kΩ 100kΩ

VCC/2

CRYSTAL

OSCILLATOR

VCC

REFSEL

Figure 18. Single-Ended REFCLK Configuration

Rev. C | Page 15 of 25

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