ADN2811 Ver la hoja de datos (PDF) - Analog Devices
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ADN2811 Datasheet PDF : 20 Pages
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The ADN2811 can accept any of the following reference clock
frequencies: 19.44 MHz, 38.88 MHz, 77.76 MHz at LVTTL/
LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/
LVDS levels via the REFCLKN/P inputs, independent of data
rate. The input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV
(e.g., LVPECL or LVDS) or a standard single-ended low voltage
TTL input, providing maximum system flexibility. The
appropriate division ratio can be selected using the REFSEL0/1
pins, according to Table 5. Phase noise and duty cycle of the
reference clock are not critical, and 100 ppm accuracy is
sufficient.
Table 5. Reference Frequency Selection
Applied Reference
REFSEL REFSEL[1..0] Frequency (MHz)
1
00
19.44
1
01
38.88
1
10
77.76
1
11
155.52
0
XX
REFCLKP/N Inactive. Use 19.44 MHz
XTAL oscillator on Pins XO1, XO2 (Pull
REFCLKP to VCC).
An on-chip oscillator to be used with an external crystal is also
provided as an alternative to using the REFCLKN/P inputs.
Details of the recommended crystal are given in Table 6.
Table 6. Required Crystal Specifications
Parameter
Value
Mode
Series Resonant
Frequency/Overall Stability
19.44 MHz ±100 ppm
Frequency Accuracy
±100 ppm
Temperature Stability
±100 ppm
Aging
±100 ppm
ESR
50 Ω max
ADN2811
REFSEL must be tied to VCC when the REFCLKN/P inputs are
active, or tied to VEE when the oscillator is used. No connection
between the XO pin and REFCLK input is necessary (see
Figure 14, Figure 15, and Figure 16). Note that the crystal should
operate in series resonant mode, which renders it insensitive to
external parasitics. No trimming capacitors are required.
LOCK DETECTOR OPERATION
The lock detector monitors the frequency difference between
the VCO and the reference clock and deasserts the loss of lock
signal when the VCO is within 500 ppm of center frequency
(see Figure 17). This enables the phase loop, which pulls the
VCO frequency in the remaining amount and also acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss of lock signal is reasserted and
control returns to the frequency loop, which reacquires and
maintains a stable clock signal at the output.
The frequency loop requires a single external capacitor between
CF1 and CF2. The capacitor specification is given in Table 7.
Table 7. Recommended CF Capacitor Specification
Parameter
Value
Temperature Range
−40°C to +85°C
Capacitance
>3.0 µF
Leakage
<80 nA
Rating
>6.3 V
LOL
1
1000
500
0
500
1000
fVCO ERROR
(ppm)
Figure 17. Transfer Function of LOL
Rev. B | Page 13 of 20
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