ADN2807(RevA) Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADN2807
(Rev.:RevA)

155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

ADN2807

ADN2807

PIN

+

QUANTIZER

0

NIN

50Ω 50Ω

VREF

1

50Ω 50Ω

FROM

QUANTIZER

OUTPUT

1

CDR

RETIMED

DATA

CLK

0

VCC

TDINP/N

LOOPEN BYPASS DATAOUTP/N

CLKOUTP/N SQUELCH

Figure 19. Test Modes

SQUELCH MODE

When the squelch input is driven to a TTL high state, both the

clock and data outputs are set to the zero state to suppress

downstream processing. If desired, this pin can be directly

driven by the LOS (loss-of-signal) detector output (SDOUT). If

the squelch function is not required, the pin should be tied to

VEE.

TEST MODES—BYPASS AND LOOP-BACK

When the bypass input is driven to a TTL high state, the

quantizer output is connected directly to the buffers driving the

data out pins, thus bypassing the clock recovery circuit

(Figure 19). This feature can help the system to deal with

nonstandard bit rates.

The loopback mode can be invoked by driving the LOOPEN

pin to a TTL high state, which facilitates system diagnostic

testing. This will connect the test inputs (TDINP/N) to the

clock and data recovery circuit (per Figure 19). The test inputs

have internal 50 Ω terminations and can be left floating when

not in use. TDINP/N are CML inputs and can be dc-coupled

only when being driven by CML outputs. The TDINP/N inputs

must be ac-coupled if driven by anything other than CML

outputs. Bypass and loop-back modes are mutually exclusive;

only one of these modes can be used at any given time. The

ADN2807 is put into an indeterminate state if both BYPASS

and LOOPEN pins are set to Logic 1 at the same time.

Rev. A | Page 14 of 20

Share Link: