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ADM6996F

6 port 10/100 Mb/s Single Chip Ethernet Switch Controller

Infineon Technologies 

.

V1.03

3.7 Carrier Sense.................................................................................................... 3-7

3.8 Jabber Function................................................................................................ 3-7

3.9 Link Test Function........................................................................................... 3-7

3.10 Automatic Link Polarity Detection.............................................................. 3-8

3.11 Clock Synthesizer ........................................................................................ 3-8

3.12 Auto Negotiation.......................................................................................... 3-8

3.13 Memory Block ............................................................................................. 3-8

3.14 Switch Functional Description..................................................................... 3-9

3.15 Basic Operation............................................................................................ 3-9

3.15.1 Address Learning ..................................................................................... 3-9

3.15.2 Address Recognition and Packet Forwarding ....................................... 3-10

3.15.3 Address Aging ........................................................................................ 3-10

3.15.4 Back off Algorithm ................................................................................. 3-10

3.15.5 Inter-Packet Gap (IPG) ......................................................................... 3-10

3.15.6 Illegal Frames........................................................................................ 3-11

3.15.7 Half Duplex Flow Control ..................................................................... 3-11

3.15.8 Full Duplex Flow Control...................................................................... 3-11

3.15.9 Broadcast Storm filter............................................................................ 3-11

3.16 Auto TP MDIX function................................................................................ 3-11

3.17 Port Locking............................................................................................... 3-12

3.18 VLAN setting & Tag/Untag & port-base VLAN ...................................... 3-12

3.19 Priority Setting ........................................................................................... 3-13

3.20 LED Display .............................................................................................. 3-13

Chapter 4 Register Description .................................................................................... 4-1

4.1 EEPROM Content............................................................................................ 4-1

4.2 EEPROM Register Map................................................................................... 4-1

4.3 EEPROM Register ........................................................................................... 4-2

4.3.1 Signature Register, offset: 0x00h.............................................................. 4-2

4.3.2 Configuration Registers, offset: 0x01h ~ 0x09h ...................................... 4-3

4.3.3 Reserved Register, offset: 0x0ah.............................................................. 4-3

4.3.4 Configuration Register, offset: 0x0bh...................................................... 4-4

4.3.5 Reserved Register, offset: 0x0ch~0x0dh .................................................. 4-4

4.3.6 VLAN priority Map Register, offset: 0x0eh ............................................. 4-4

4.3.7 TOS priority Map Register, offset: 0x0fh................................................. 4-4

4.3.8 Packet with Priority: Normal packet content .......................................... 4-5

4.3.9 VLAN Packet............................................................................................ 4-5

4.3.10 TOS IP Packet.......................................................................................... 4-1

4.3.11 Miscellaneous Configuration Register, offset: 0x10h.............................. 4-1

4.3.12 VLAN mode select Register, offset: 0x11h............................................... 4-2

4.3.13 Miscellaneous Configuration register, offset: 0x12h .............................. 4-4

4.3.14 VLAN mapping table registers, offset: 0x22h ~ 0x13h ............................ 4-4

4.3.15 Reserved Register, offset: 0x27h ~ 0x23h................................................ 4-4

4.3.16 Port0, 1 PVID bit 11 ~ 4 Configuration Register, offset: 0x28h ............. 4-1

4.3.17 Port2, 3 PVID bit 11 ~ 4 Configuration Register, offset: 0x29h ............. 4-1

4.3.18 Port4, 5 PVID bit 11~4 Configuration Register, offset: 0x2ah ............... 4-1

4.3.19 Port6, 7 PVID bit 11~4 Configuration Register, offset: 0x2bh ............... 4-1

ADM6996F

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