ADM1034ARQZ-REEL(2012) Ver la hoja de datos (PDF) - ON Semiconductor
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ADM1034ARQZ-REEL Datasheet PDF : 38 Pages
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ADM1034
Table 6. RESISTOR RATIOS FOR SETTING LOCATION BITS
Ideal Ratio R2/(R1 + R2) R1 kW R2 W Actual R2/(R1 + R2) Error %
N/A
0
O/C
1
0
0.8125
18
82
0.82
+0.75
0.6875
22
47
0.6812
−0.63
0.5625
12
15
0.5556
−0.69
0.4375
15
12
0.4444
+0.69
0.3125
47
22
0.3188
+0.63
0.1875
82
18
0.18
−0.75
N/A
O/C
0
0
0
1. ARP denotes ARP-capable mode, FD denotes fixed and discoverable mode.
SMBus Ver
(Note 1)
ARP
ARP
ARP
ARP
FD
FD
FD
FD
SMBus Address
N/A
N/A
N/A
N/A
0x53
0x52
0x51
0x50
UDID LLL
111
110
101
100
N/A
N/A
N/A
N/A
Table 7. UDID VALUES
Bit No.
Name
<127:120> Device Capabilities
<119:112>
<111:96>
Version/Revision
Vendor ID
<95:80> Device ID
<79:64> Interface
<63:48> Subsystem Vendor ID
<47:32> Subsystem Device ID
<31:0>
Vendor Specific ID
Function
Describes the ADM1034’s capabilities (for instance, that it supports
PEC and uses a random number address device).
UDID version number (Version 1) and silicon revision identification
Analog Devices vendor ID number, as assigned by the SBS
Implementer’s Forum or the PCI SIG.
Device ID.
Identifies the protocol layer interfaces supported by the ADM1034.
This represents SMBus 2.0 as the Interface version..
Subsystem Vendor ID = 0 (subsystem fields are unsupported).
Subsystem Device ID = 0 (subsystem fields are unsupported).
A unique number per device. Contains LOCATION information (LL)
and a 16-bit random number (x). See Table 9 for information on
setting the LLL bits.
Value
11000001
00001010
00010001
11010100
00010000
00110100
00000000
00000100
00000000
00000000
00000000
00000000
00000000
00000LLL
xxxxxxxx
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SMBus 2.0 Fixed and Discoverable Mode
The ADM1034 also supports fixed and discoverable
mode, which is backwards compatible with SMBus 1.0 and
1.1. Fixed and discoverable mode supports all the same
functionality as ARP-capable mode, except for assign
address in which case it powers up with a fixed address and
is not changed by the assign address call. The fixed address
is determined by the state of the LOCATION pin on
powerup.
SMBus 2.0 Read and Write Operations
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line (SDA) while the serial clock line (SCL) remains
high. This indicates that an address/data stream is to follow.
All slave peripherals connected to the serial bus respond to
the start condition and shift in the next 8 bits, which consist
of a 7-bit address (MSB first) plus an R/W bit. This last bit
determines the direction of the data transfer (whether data is
written to or read from the slave device).
1. The peripheral that corresponds to the transmitted
address responds by pulling the data line low
during the low period before the 9th clock pulse,
which is known as the acknowledge bit. All other
devices on the bus remain idle while the selected
device waits for data to be read from or written to
it. If the R/W bit is a 0, the master writes to the
slave device. If the R/W bit is a 1, the master reads
from it.
2. Data is sent over the serial bus in sequences of 9
clock pulses − 8 bits of data followed by an
acknowledge bit from the slave device. Transitions
on the data line must occur during the low period
of the clock signal and remain stable during the
high period, because a low-to-high transition when
the clock is high may be interpreted as a stop
signal. The number of data bytes that can be
transmitted over the serial bus in a single read or
write operation is limited only by what the master
and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the 10th
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