ADL5357 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADL5357

500 MHz to 1700 MHz Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun

Analog Devices 

ADL5357

CIRCUIT DESCRIPTION

The ADL5357 consists of two primary components: the radio

frequency (RF) subsystem and the local oscillator (LO) subsystem.

The combination of design, process, and packaging technology

allows the functions of these subsystems to be integrated

into a single die, using mature packaging and interconnection

technologies to provide a high performance, low cost design

with excellent electrical, mechanical, and thermal properties.

In addition, the need for external components is minimized,

optimizing cost and size.

The RF subsystem consists of an integrated, low loss RF balun,

passive MOSFET mixer, sum termination network, and IF

amplifier.

The LO subsystem consists of an SPDT-terminated FET switch

and a three-stage limiting LO amplifier. The purpose of the LO

subsystem is to provide a large, fixed amplitude, balanced signal

to drive the mixer independent of the level of the LO input.

A block diagram of the device is shown in Figure 51.

IFGM

20

IFOP

19

IFON

18

PWDN

17

LEXT

16

VPIF 1

ADL5357

15 LOI2

RFIN 2

14 VPSW

RFCT 3

COMM 4

BIAS

GENERATOR

13 VGS1

12 VGS0

COMM 5

6

VLO3

NC = NO CONNECT

7

LGM3

8

VLO2

9

LOSW

Figure 51. Simplified Schematic

11 LOI1

10

NC

RF SUBSYSTEM

The single-ended, 50 Ω RF input is internally transformed to a

balanced signal using a low loss (<1 dB) unbalanced-to-balanced

(balun) transformer. This transformer is made possible by an

extremely low loss metal stack, which provides both excellent

balance and dc isolation for the RF port. Although the port can

be dc connected, it is recommended that a blocking capacitor be

used to avoid running excessive dc current through the part.

The RF balun can easily support an RF input frequency range

of 500 MHz to 1700 MHz.

The resulting balanced RF signal is applied to a passive mixer

that commutates the RF input with the output of the LO subsystem.

The passive mixer is essentially a balanced, low loss switch that

adds minimum noise to the frequency translation. The only

noise contribution from the mixer is due to the resistive loss

of the switches, which is in the order of a few ohms.

Because the mixer is inherently broadband and bidirectional, it

is necessary to properly terminate all the idler (M × N product)

frequencies generated by the mixing process. Terminating the

mixer avoids the generation of unwanted intermodulation

products and reduces the level of unwanted signals at the input

of the IF amplifier, where high peak signal levels can compromise

the compression and intermodulation performance of the system.

This termination is accomplished by the addition of a sum

network between the IF amplifier and the mixer and also in

the feedback elements in the IF amplifier.

The IF amplifier is a balanced feedback design that simultaneously

provides the desired gain, noise figure, and input impedance that are

required to achieve the overall performance. The balanced open-

collector output of the IF amplifier, with impedance modified

by the feedback within the amplifier, permits the output to be

connected directly to a high impedance filter, differential amplifier,

or an analog-to-digital input while providing optimum second-

order intermodulation suppression. The differential output

impedance of the IF amplifier is approximately 200 Ω. If operation

in a 50 Ω system is desired, the output can be transformed to

50 Ω by using a 4:1 transformer.

The intermodulation performance of the design is generally

limited by the IF amplifier. The IP3 performance can be optimized

by adjusting the IF current with an external resistor. Figure 41,

Figure 43, and Figure 44 illustrate how various IF and LO bias

resistors affect the performance with a 5 V supply. Additionally,

dc current can be saved by increasing either or both resistors. It

is permissible to reduce the dc supply voltage to as low as 3.3 V,

further reducing the dissipated power of the part. (Note that no

performance enhancement is obtained by reducing the value of

these resistors, and excessive dc power dissipation may result.)

Rev. 0 | Page 16 of 24

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