ADF7010BRU Ver la hoja de datos (PDF) - Analog Devices
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ADF7010BRU Datasheet PDF : 20 Pages
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ADF7010
0.00
0.20
0.50
0.0
1.00
2.00
5.00
M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1
12-BIT N VALUE
؊0.20
؊150
L(SHUNT) = 12nH
L(SERIES) = 6.8nH
؊5.00
؊30
؎ F10 F9 F8 F7 F6 F5 F4 F3 F2 F1
10-BIT (؉ SIGN) ERROR CORRECTION
؊140
؊130
؊0.50
16 – j33
؊40
؊2.00
؊50
N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
15-BIT FRACTIONAL N REGISTER
؊120
؊110
؊1.00
؊60
؊70
Figure 12. Fractional Components
؊100 ؊90 ؊80
Figure 10. Output Impedance on Smith Chart
FRACTIONAL-N
N COUNTER AND ERROR CORRECTION
The ADF7010 consists of a 15-bit sigma-delta fractional N
E divider. The N Counter divides the output frequency to the output
stage back to the PFD frequency. It consists of a prescaler, integer,
and fractional part.
T The prescaler can be 4/5 or 8/9. The spurious performance is
better with a 4/5 prescaler, and the N-value can be lower since
NMIN is P 2 + 3P + 3.
The output frequency of the PLL is:
E PFD
Frequency
¥
Int
+ (23
¥
Fractional
215
)
+
Error
L REFERENCE IN
،R
PFD/
CHARGE
PUMP
VCO
O ،N
THIRD ORDER
⌺-⌬ MODULATOR
S FRACTIONAL N
INTEGER N
B Figure 11. Fractional-N PLL
Fractional-N Registers
The fractional part is made up of a 15-bit divide, made up of
O a 12-bit N value in the N Register summed with a 10-bit (plus
The resolution of each register is the smallest amount that the
output frequency can be changed by changing the LSB of the
register.
Changing the Output Frequency
The fractional part of the N Register changes the output fre-
quency by:
(FPFD )(N-Register Value)
212
The frequency error correction contained in the R Register
changes the output frequency by:
(FPFD )(Frequency Error Correction Value)
215
By default, this will be set to 0. The user can calibrate the system
and set this by writing a twos complement number to Bits F1–F11
in the R Register. This can be used to compensate for initial error,
temperature drift, and aging effects in the crystal reference.
Integer N Register
The integer part of the N-Counter contains the prescaler and A and
B counters. It is eight bits wide and offers a divide of P 2 + 3P + 3
to 255.
The combination of the integer (255) and the fractional (31767/
31768) give a maximum N Divider of 256. The minimum PFD
usable is:
FPFD (min) =
Maximum Output Frequency Required
(255 + 1)
For use in the U.S. 902 MHz–928 MHz band, there is a restriction
to using a minimum PFD of 3.625 MHz to allow the user to have
a center frequency of 928 MHz.
PFD Frequency
sign bit) in the R-Register that is used for error correction, as
The PFD frequency is the number of times a comparison is
shown in Figure 12.
made between the reference frequency and the feedback signal
from the output.
The higher the PFD frequency, the more often a comparison is
made at the PFD. This also allows a wider loop bandwidth
without compromising stability. This means that the frequency
lock time will be reduced when jumping from one frequency to
another by increasing the PFD.
–18–
REV. 0
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