ADE7769 Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

ADE7769

Energy Metering IC with Integrated Oscillator and No-Load Indication

Analog Devices 

ADE7769

RA* RB

RF

V2P

CF ±165mV V2N

RF

CF

NEUTRAL PHASE

*RA >> RB + RF

Figure 20. Typical Connections for Channel V2

POWER SUPPLY MONITOR

The ADE7769 contains an on-chip power supply monitor. The

power supply (VDD) is continuously monitored by the ADE7769.

If the supply is less than 4 V, the ADE7769 becomes inactive.

This is useful to ensure proper device operation at power-up

and power-down. The power supply monitor has built-in

hysteresis and filtering, which provide a high degree of

immunity to false triggering from noisy supplies.

In Figure 21, the trigger level is nominally set at 4 V. The toler-

ance on this trigger level is within ±5%. The power supply and

decoupling for the part should be such that the ripple at VDD

does not exceed 5 V ± 5%, as specified for normal operation.

VDD

5V

4V

0V

TIME

INTERNAL

ACTIVATION INACTIVE

ACTIVE

INACTIVE

Figure 21. On-Chip Power Supply Monitor

HPF and Offset Effects

Figure 22 shows the effect of offsets on the real power calcula-

tion. As can be seen, offsets on Channel V1 and Channel V2

contribute a dc component after multiplication. Because this dc

component is extracted by the LPF and used to generate the real

power information, the offsets contribute a constant error to the

real power calculation. This problem is easily avoided by the

built-in HPF in Channel V1. By removing the offsets from at

least one channel, no error component can be generated at dc

by the multiplication. Error terms at the line frequency (ω) are

removed by the LPF and the digital-to-frequency conversion

(see the Digital-to-Frequency Conversion section).

Equation 6 shows how the power calculation is affected by the

dc offsets in the current and voltage channels.

{V cos (ωt ) + VOS } × {I cos (ωt ) + IOS }

(6)

=

V×I

2

+ VOS

× IOS

+ VOS

×I

cos(ωt ) +

IOS

×V cos(ωt )

+ V × I × cos(2ωt )

2

VOS × IOS

V× I

2

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL

POWER CALCULATION

IOS × V

VOS × I

0

FREQUENCY (RAD/s)

Figure 22. Effect of Channel Offset on the Real Power Calculation

The HPF in Channel V1 has an associated phase response that

is compensated for on chip. Figure 23 and Figure 24 show the

phase error between channels with the compensation network

activated. The ADE7769 is phase compensated up to 1 kHz as

shown. This ensures correct active harmonic power calculation

even at low power factors.

0.30

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (Hz)

Figure 23. Phase Error Between Channels (0 Hz to 1 kHz)

Rev. A | Page 12 of 20

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