ADE7756 Ver la hoja de datos (PDF) - Analog Devices
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ADE7756 Datasheet PDF : 32 Pages
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ADE7756
INTERRUPTS
Interrupts are managed through the Interrupt Status register
(STATUS[7:0]) and the Interrupt Enable register (IRQEN[7:0]).
When an interrupt event occurs in the ADE7756, the corre-
sponding flag in the Status register is set to a Logic 1—see
Interrupt Status register. If the enable bit for this interrupt in
the Interrupt Enable register is Logic 1, the IRQ logic output
goes active low. The flag bits in the Status register are set irre-
spective of the state of the enable bits.
In order to determine the source of the interrupt, the system mas-
ter (MCU) should perform a read from the Status register with
reset (RSTATUS[7:0]). This is achieved by carrying out a read
from address 05h. The IRQ output will go logic high on comple-
tion of the Interrupt Status register read command—see Interrupt
Timing section. When carrying out a read with reset the ADE7756
is designed to ensure that no interrupt events are missed. If an
interrupt event occurs just as the Status register is being read,
the event will not be lost and the IRQ logic output is guaranteed
to go high for the duration of the Interrupt Status register data
transfer before going logic low again to indicate the pending
interrupt. See the next section for a more detailed description.
Using the ADE7756 Interrupts with an MCU
Shown in Figure 11 is a timing diagram that shows a sug-
gested implementation of ADE7756 interrupt management
using an MCU. At time t1 the IRQ line will go active low indi-
cating that one or more interrupt events have occurred in the
ADE7756. The IRQ logic output should be tied to a negative
edge-triggered external interrupt on the MCU. On detection of
the negative edge, the MCU should be configured to start execut-
ing its Interrupt Service Routine (ISR). On entering the ISR, all
interrupts should be disabled using the global interrupt enable
bit. At this point the MCU external interrupt flag can be cleared
in order to capture interrupt events that occur during the current
ISR. When the MCU interrupt flag is cleared a read from the
Status register with reset is carried out. This will cause the IRQ
line to be reset logic high (t2)—see Interrupt timing section. The
Status register contents are used to determine the source of the
interrupt(s) and hence the appropriate action to be taken. If a
subsequent interrupt event occurs during the ISR, that event will
be recorded by the MCU external interrupt flag being set again
(t3). On returning from the ISR, the global interrupt mask will
be cleared (same instruction cycle) and the external interrupt
flag will cause the MCU to jump to its ISR once again. This will
ensure that the MCU does not miss any external interrupts.
Interrupt Timing
The Serial Interface section should be reviewed first, before
reviewing the interrupt timing. As previously described, when
the IRQ output goes low the MCU ISR must read the Interrupt
Status register in order to determine the source of the interrupt.
When reading the Status register contents, the IRQ output is set
high on the last falling edge of SCLK of the first byte transfer
(read Interrupt Status register command). The IRQ output is
held high until the last bit of the next 8-bit transfer is shifted out
(Interrupt Status register contents). See Figure 12. If an inter-
rupt is pending at this time, the IRQ output will go low again. If
no interrupt is pending the IRQ output will stay high.
t1
IRQ
MCU
INTERRUPT
t2
t3
FLAG SET
MCU
PROGRAM
SEQUENCE
CS
SCLK
DIN
DOUT
IRQ
JUMP
TO
ISR
GLOBAL
INTERRUPT
MASK SET
CLEAR MCU
INTERRUPT
FLAG
READ
STATUS WITH
RESET (05h)
ISR ACTION
(BASED ON
STATUS CONTENTS)
Figure 11. Interrupt Management
ISR RETURN
GLOBAL INTERRUPT
MASK RESET
JUMP
TO
ISR
t1
t9
0
00
00
1
01
t11
t11
DB7
READ STATUS REGISTER COMMAND
STATUS REGISTER CONTENTS
DB0
Figure 12. Interrupt Timing
REV. 0
–15–
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