AD9866 Ver la hoja de datos (PDF) - Analog Devices
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AD9866 Datasheet PDF : 48 Pages
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AD9866
SERIAL PORT TIMING SPECIFICATIONS
Table 5. AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted
Parameter
Temp
Test Level
Min Typ
WRITE OPERATION (See Figure 46)
SCLK Clock Rate (fSCLK)
Full
IV
SCLK Clock High (tHI)
Full
IV
14
SCLK Clock Low (tLOW)
Full
IV
14
SDIO to SCLK Setup Time (tDS)
Full
IV
14
SCLK to SDIO Hold Time (tDH)
Full
IV
0
SEN to SCLK Setup Time (tS)
Full
IV
14
SCLK to SEN Hold Time (tH)
Full
IV
0
READ OPERATION (See Figure 47 and Figure 48)
SCLK Clock Rate (fSCLK)
Full
IV
SCLK Clock High (tHI)
Full
IV
14
SCLK Clock Low (tLOW)
Full
IV
14
SDIO to SCLK Setup Time (tDS)
Full
IV
14
SCLK to SDIO Hold Time (tDH)
Full
IV
0
SCLK to SDIO (or SDO) Data Valid Time (tDV)
Full
IV
SEN to SDIO Output Valid to Hi-Z (tEZ)
Full
IV
2
Max Unit
32
MHz
ns
ns
ns
ns
ns
ns
32
MHz
ns
ns
ns
ns
14
ns
ns
HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS
Table 6. AVDD = 3.3 V ±5%, DVDD = CLKVDD = DRVDD = 3.3 V ±10%, unless otherwise noted
Parameter
Temp Test Level
Min Typ Max
READ OPERATION (See Figure 50)
Output Data Rate
Full
II
5
80
Three-State Output Enable Time (tPZL)
Full
II
80
Three-State Output Disable Time (tPLZ)
Full
II
3
Rx Data Valid Time (tDV)
Full
II
3
Rx Data Output Delay (tOD)
Full
II
4
WRITE OPERATION (See Figure 49)
Input Data Rate (1× Interpolation)
Full
II
20
80
Input Data Rate (2× Interpolation)
Full
II
10
80
Input Data Rate (4× Interpolation)
Full
II
5
50
Tx Data Setup Time (tDS)
Full
II
12.5
Tx Data Hold Time (tDH)
Full
II
0
Latch Enable Time (tEN)
Full
II
3
Latch Disable Time (tDIS)
Full
II
3
Unit
MSPS
ns
ns
ns
ns
MSPS
MSPS
MSPS
ns
ns
ns
ns
Rev. 0 | Page 7 of 48
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