AD9866 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
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Fabricante
AD9866 Datasheet PDF : 48 Pages
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AD9866
Parameter
Rx Mode
IAVDD + ICLKVDD
IDVDD + IDRVDD
POWER CONSUMPTION OF FUNCTIONAL BLOCKS1 (IAVDD + ICLKVDD)
RxPGA and LPF
ADC
TxDAC
IAMP (Programmable)
Reference
CLK PLL and Synthesizer
MAXIMUM ALLOWABLE POWER DISSIPATION
STANDBY POWER CONSUMPTION
IS_TOTAL (Total Supply Current)
POWER DOWN DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and Synthesizer
POWER UP DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and Synthesizer
Temp Test Level Min Typ Max Unit
25°C
225
253
mA
25°C
36.5 39
mA
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
Full IV
87
mA
108
mA
38
mA
10
120
mA
170
mA
107
mA
1.66 W
Full
13
mA
25°C III
25°C III
25°C III
25°C III
25°C III
440
ns
12
ns
20
ns
20
ns
27
ns
25°C III
25°C III
25°C III
25°C III
25°C III
7.8
µs
88
ns
13
µs
20
ns
20
µs
1Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP’s current consumption, which is application dependent.
2Default power-up settings for MODE = LOW and CONFIG = LOW .
DIGITAL SPECIFICATIONS
Table 4. AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; RSET = 2 kΩ, unless otherwise noted
Parameter
Temp Test Level Min
Typ Max
CMOS LOGIC INPUTS
High Level Input Voltage
Full
VI
DRVDD – 0.7
Low Level Input Voltage
Full
VI
0.4
Input Leakage Current
12
Input Capacitance
Full
VI
3
CMOS LOGIC OUTPUTS (CLOAD = 5 pF)
High Level Output Voltage (IOH = 1 mA)
Full
VI
DRVDD – 0.7
Low Level Output Voltage (IOH = 1 mA)
Full
VI
1.2
2
Output Rise/Fall Time (High Strength Mode and CLOAD = 15 pF) Full
VI
1.5/2.3
Output Rise/Fall Time (Low Strength Mode and CLOAD = 15 pF) Full
VI
1.9/2.7
Output Rise/Fall Time (High Strength Mode and CLOAD = 5 pF)
Full
VI
0.7/0.7
Output Rise/Fall Time (Low Strength Mode and CLOAD = 5 pF)
Full
VI
1.0/1.0
RESET
Minimum Low Pulse Width (Relative to fADC)
1
Unit
V
V
µA
pF
ns
ns
ns
ns
Clock
cycles
Rev. 0 | Page 6 of 48
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