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Fabricante

AD9824

Complete 14-Bit 30 MSPS CCD Signal Processor

Analog Devices 

SERIAL 3

INTERFACE

3V

ANALOG SUPPLY

0.1␮F

1.0␮F

1.0␮F

AD9824

DATA 14

OUTPUTS

D2 1

D3 2

D4 3

D5 4

D6 5

D7 6

D8

7

D9

8

D10

9

D11

10

D12

11

(MSB) D13

12

48 47 46 45 44 43 42 41 40 39 38 37

PIN 1

IDENTIFIER

AD9824

TOP VIEW

(Not to Scale)

AUX1IN

36

AVSS

35

AUX2IN

34

33 AVDD2

BYP3

32

31 NC

CCDIN

30

29 BYP2

28 BYP1

AVDD1

27

AVSS

26

AVSS

25

13 14 15 16 17 18 19 20 21 22 23 24

0.1␮F

0.1␮F

3V

ANALOG SUPPLY

0.1␮F

0.1␮F

CCD SIGNAL

0.1␮F

0.1␮F

3V

ANALOG SUPPLY

3V

DRIVER

SUPPLY

0.1␮F

NC = NO CONNECT

8

CLOCK

INPUTS

0.1␮F

3V

ANALOG SUPPLY

Figure 33. Recommended Circuit Configuration for CCD-Mode

Internal Power-On Reset Circuitry

After power-on, the AD9824 will automatically reset all internal

registers and perform internal calibration procedures. This takes

approximately 1 ms to complete. During this time, normal

clock signals and serial write operations may occur. However,

serial register writes will be ignored until the internal reset opera-

tion is completed.

Grounding and Decoupling Recommendations

As shown in Figure 33, a single ground plane is recommended

for the AD9824. This ground plane should be as continuous as

possible, particularly around Pins 25 through 39. This will

ensure that all analog decoupling capacitors provide the lowest

possible impedance path between the power and bypass pins and

their respective ground pins. All decoupling capacitors should

be located as close as possible to the package pins. A single clean

power supply is recommended for the AD9824, but a separate

digital driver supply may be used for DRVDD (Pin 13). DRVDD

should always be decoupled to DRVSS (Pin 14), which should

be connected to the analog ground plane. Advantages of using

a separate digital driver supply include using a lower voltage

(2.7 V) to match levels with a 2.7 V ASIC, and reducing digital

power dissipation and potential noise coupling. If the digital

outputs (Pins 1–12) must drive a load larger than 20 pF, buff-

ering is recommended to reduce digital code transition noise.

Alternatively, placing series resistors close to the digital out-

put pins may also help reduce noise.

REV. 0

–21–

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