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AD9683

14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter

Analog Devices 

Data Sheet

JESD204B Device Identification (DID) Configuration

(Address 0x64)

Bits[7:0]—JESD204B device identification (DID) value

JESD204B Bank Identification (BID) Configuration

(Address 0x65)

Bits[7:4]—Open

Bits[3:0]—JESD204B bank identification (BID) value

JESD204B Lane Identification (LID) Configuration

(Address 0x67)

Bits[7:5]—Open

Bits[4:0]—JESD204B lane identification (LID) value

JESD204B Scrambler (SCR) and Lane (L) Configuration

(Address 0x6E)

Bit 7—JESD204B scrambling (SCR)

When this bit is set to low, it disables the scrambler (SCR = 0).

When this bit is set to high, it enables the scrambler (SCR = 1).

Bits[6:5]—Open

Bits[4:0]—JESD204B number of lanes (L)

0 = one lane per link (L = 1).

JESD204B Parameter, F (Address 0x6F, Read Only)

Bits[7:0]—JESD204B number of octets per frame (F)

The readback from this register is calculated from the following

equation: F = (M × 2)/L.

The valid value for F is F = 2, with M = 1 and L = 1.

JESD204B Parameter, K (Address 0x70)

Bits[7:0]—JESD204B Number of Frames per Multiframe (K)

This register sets the K value for the JESD204B interface which

defines the number of frames per multiframe. The value must

be a multiple of 4.

JESD204B Parameter, M (Address 0x71)

Bits[7:0]—JESD204B Number of Converters (M)

0 = link connected to one ADC. Only primary input used (M = 1).

JESD204B Parameters, N/CS (Address 0x72)

Bits[7:6]—Number of control bits (CS)

00 = no control bits sent per sample (CS = 0).

01 = one control bit sent per sample—overrange bit enabled

(CS = 1).

10 = two control bits sent per sample—overflow/underflow bits

enabled (CS = 2).

Bits[5:4]—Open

Bits [3:0]—ADC converter resolution (N)

Read only bits showing the converter resolution (reads back 13

(0xD) for 14-bit resolution).

AD9683

JESD204B Parameter, Subclass/N’ (Address 0x73)

Bit 7—Reserved

Bits[6:5]—JESD204B subclass

When Bits[6:5] are 00, the device operates in Subclass 0 mode, and

when Bits[6:5] are 01, the device operates in Subclass 1 mode.

Bit 4—Reserved

Bits[3:0]—JESD204B N’ value

Read only bits showing the total number of bits per sample,

minus 1 (reads back 15 (0xF) for 16 bits per sample).

JESD204B Samples per Converter per Frame Cycle (S)

(Address 0x74)

Bits[7:6]—Open

Bit 5—Reserved; set to 1

Bits[4:0]—JESD204B samples per converter per frame per

cycle (S)

Read only bits showing the number of samples per converter

frame cycle, minus 1 (reads back 0 (0x0) for one sample per

converter frame).

JESD204B Parameters HD and CF (Address 0x75)

Bit 7—JESD204B high density (HD) value (read only)

Read only bit. Always set to 0.

Bits[6:5]—Open

Bits[4:0]—JESD204B control words per frame clock cycle per

link (CF)

Read only bits. Reads back 0x0.

JESD204B Reserved 1 (Address 0x76)

Bits[7:0]—JESD204B Reserved Field 1

This read/write register is available for customer use.

JESD204B Reserved 2 (Address 0x77)

Bits[7:0]—JESD204B Reserved Field 2

This read/write register is available for customer use.

JESD204B Checksum (Address 0x79)

Bits[7:0]—JESD204B checksum value for the output lane

This read only register is automatically calculated for the lane.

Checksum equals sum (all link configuration parameters for the

lane) modulus 256.

JESD204B Output Driver Control (Address 0x80)

Bits[7:1]—Reserved

Bit 1—JESD204B driver power-down

When this bit is set low, the JESD204B output drivers are enabled.

When this bit is set high, the JESD204B output drivers are

powered down.

Rev. 0 | Page 41 of 44

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