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AD9525

Low Jitter Clock Generator with Eight LVPECL Outputs

Analog Devices 

AD9525

THEORY OF OPERATION

The AD9525 PLL is useful for generating clock frequencies from

a supplied reference frequency. In addition, the PLL can be used

to clean up jitter and phase noise on a noisy reference. The exact

choice of PLL parameters and loop dynamics is application specific.

The flexibility and depth of the AD9525 PLL allow the part to

be tailored to function in many different applications and signal

environments.

The AD9525 includes on-chip PLL blocks that can be used with

an external VCO or VCXO to create a complete phase-locked

loop. The PLL requires an external loop filter, which usually

consists of a small number of capacitors and resistors. The

configuration and components of the loop filter help to establish

the loop bandwidth and stability of the PLL. The external loop

filter that must be connected between CP and the tuning pin of

the VCO/VCXO. This loop filter determines the loop bandwidth

and stability of the PLL. Make sure to select the proper PFD

polarity for the VCO/VCXO being used.

The AD9525 can also be configured as a clock distribution by

shutting down the PLL and using CLKIN and CLKIN as the

input. The M divider can be used to divide the input frequency

down to the desired output frequency to each of the eight LVPECL

outputs.

CONFIGURATION OF THE PLL

Configuration of the PLL is accomplished by programming

the various settings for the R divider, N divider, PFD polarity,

and charge pump current. The combination of these settings

and the loop filter determines the PLL loop bandwidth and PLL

stability. These are managed through programmable register

settings and by the design of the external loop filter.

Successful PLL operation and satisfactory PLL loop performance

are highly dependent on proper configuration of the PLL settings,

and the design of the external loop filter is crucial to the proper

operation of the PLL.

ADIsimCLK™ is a free program that can help with the design

and exploration of the capabilities and features of the AD9525,

including the design of the PLL loop filter. The AD9516 model

found in ADIsimCLK Version 1.2 can also be used for modeling

the AD9525 loop filter. It is available at www.analog.com/clocks.

Phase Frequency Detector (PFD)

The PFD takes inputs from the R divider and the N divider and

produces an output proportional to the phase and frequency

difference between them. The PFD includes a programmable

delay element that controls the width of the antibacklash pulse.

This pulse ensures that there is no dead zone in the PFD transfer

function and minimizes phase noise and reference spurs. The

antibacklash pulse width is set by Register 0x010[1:0].

Data Sheet

An important limit to keep in mind is the maximum frequency

allowed into the PFD. The maximum input frequency into the

PFD is a function of the antibacklash pulse setting, as specified

in the phase/frequency detector (PFD) parameter in Table 7.

Charge Pump (CP)

The charge pump is controlled by the PFD. The PFD monitors

the phase and frequency relationship between its two inputs and

tells the CP to pump up or pump down to charge or discharge the

integrating node (part of the loop filter). The integrated and

filtered CP current is transformed into a voltage that drives the

tuning node of the external VCO to move the VCO frequency

up or down. The CP can be set for high impedance (allows

holdover operation), for normal operation (attempts to lock the

PLL loop), for pump-up, or for pump-down (test modes). The CP

current is programmable in eight steps. The exact value of the CP

current LSB is set by the CPRSET resistor, which is nominally

5.1 kΩ. The actual LSB current can be calculated by CP_LSB =

3.06/CPRSET.

PLL External Loop Filter

An example of an external loop filter for the PLL is shown in

Figure 19. A loop filter must be calculated for each desired PLL

configuration. The values of the components depend on the VCO

frequency, the KVCO, the PFD frequency, the charge pump

current, the desired loop bandwidth, and the desired phase

margin. The loop filter affects the phase noise, the loop settling

time, and the loop stability. A basic knowledge of PLL theory is

necessary for understanding loop filter design. ADIsimCLK can

help with the calculation of a loop filter according to the application

requirements.

PLL Reference Inputs

The AD9525 features two fully differential PLL reference input

circuits. The differential inputs are self-biased, allowing for easy

ac coupling of input signals. All PLL reference inputs are off by

default. The self-bias level of the two sides is offset slightly to

prevent chattering of the input buffer when the reference is ac

coupled and is slow or missing. The input offset increases the

voltage swing required of the driver to overcome the offset. The

input frequency range and common-mode voltages for the

reference inputs are specified in Table 4.

The reference input receiver is powered down when the PLL is

powered down. It is possible to dc couple to these inputs. If the

differential reference input is driven by a single-ended signal,

the unused side (REFA or REFB) should be decoupled via a

suitable capacitor to a quiet ground.

The AD9525 provides a third single-ended CMOS reference

input referred to as REFC.

Rev. A | Page 20 of 48

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