AD9445 Ver la hoja de datos (PDF) - Analog Devices

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AD9445

14-Bit, 105/125 MSPS, IF Sampling ADC

Analog Devices 

AD9445

OPERATIONAL MODE SELECTION

Data Format Select

The data format select (DFS) pin of the AD9445 determines

the coding format of the output data. This pin is 3.3 V CMOS-

compatible, with logic high (or AVDD1, 3.3 V) selecting twos

complement and DFS logic low (AGND) selecting offset binary

format. Table 10 summarizes the output coding.

Output Mode Select

The OUPUT MODE pin controls the logic compatibility, as well

as the pinout of the digital outputs. This pin is a CMOS-compatible

input. With OUTPUT MODE = 0 (AGND), the AD9445 outputs

are CMOS compatible, and the pin assignment for the device is

as defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3

V), the AD9445 outputs are LVDS compatible, and the pin

assignment for the device is as defined in Table 7.

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS MODE pin; a CMOS

logic low (AGND) on DCS MODE enables the DCS, and logic

high (AVDD1, 3.3 V) disables the controller.

RF ENABLE

The RF ENABLE pin is a CMOS-compatible control pin that

optimizes the configuration of the AD9445 analog front end.

The crossover analog input frequency for determining the

RF ENABLE connection differs for the 105 MSPS and 125 MSPS

speed grades. For the 125 MSPS speed grade, connecting the

RF ENABLE to AGND optimizes SFDR performance for appli-

cations with analog input frequencies <210 MHz. For applications

with analog inputs >210 MHz, this pin should be connected to

AVDD1 for optimum SFDR performance. Connecting this pin to

AVDD1 reconfigures the ADC, thereby improving high IF and RF

spurious performance. Operating in this mode increases power dis-

sipation from AVDD2 by 150 mW to 200 mW. For the 105 MSPS

speed grade, connecting RF ENABLE to AGND optimizes SFDR

performance for applications with analog input frequencies

<230 MHz. For applications with analog inputs >230 MHz, this

pin should be connected to AVDD1 to optimize performance.

Table 10. Digital Output Coding

VIN+ − VIN−

Code Input Span = 3.2 V p-p (V)

16,383 +1.600

8192 0

8191 −0.000195

0

−1.60

VIN+ − VIN−

Input Span = 2 V p-p (V)

+1.000

0

−0.000122

−1.00

Digital Output

Offset Binary (D13••••••D0)

11 1111 1111 1111

10 0000 0000 0000

01 1111 1111 1111

00 0000 0000 0000

Digital Output

Twos Complement (D13••••••D0)

01 1111 1111 1111

00 0000 0000 0000

11 1111 1111 1111

10 0000 0000 0000

Rev. 0 | Page 28 of 40

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