AD8137(2004) Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

AD8137
(Rev.:2004)

Low Cost, Low Power, Differential ADC Driver

Analog Devices 

Estimating DC Errors

Primary differential output offset errors in the AD8137 are due

to three major components: the input offset voltage, the offset

between the VAN and VAP input currents interacting with the

feedback network resistances, and the offset produced by the dc

voltage difference between the input and output common-mode

voltages in conjunction with matching errors in the feedback

network.

The first output error component is calculated as

Vo_e 1

=

VIO

⎜⎛

⎝

RF + RG

RG

⎟⎞

⎠

,

or

equivalently

as

VIO/β

(21)

where VIO is the input offset voltage.

The second error is calculated as

Vo_e

2

=

I

IO

⎜⎛

⎝

RF + RG

RG

⎟⎞⎜⎛

⎠⎝

RGRF

RF + RG

⎟⎞

⎠

=

IIO (RF

)

(22)

where IIO is defined as the offset between the two input bias

currents.

The third error voltage is calculated as

Vo_e 3 = ∆enr × (VICM − VOCM )

(23)

where Δenr is the fractional mismatch between the two feed-

back resistors.

The total differential offset error is the sum of these three error

sources.

Additional Impact of Mismatches in the Feedback Networks

The internal common-mode feedback network will still force

the output voltages to remain balanced, even when the RF/RG

feedback networks are mismatched. The mismatch will, how-

ever, cause a gain error proportional to the feedback network

mismatch.

Ratio-matching errors in the external resistors will degrade the

ability to reject common-mode signals at the VAN and VIN input

terminals, much the same as with a four-resistor difference

amplifier made from a conventional op amp. Ratio-matching

errors will also produce a differential output component that is

equal to the VOCM input voltage times the difference between the

feedback factors (βs). In most applications using 1% resistors,

this component amounts to a differential dc offset at the output

that is small enough to be ignored.

AD8137

Driving a Capacitive Load

A purely capacitive load will react with the bondwire and pin

inductance of the AD8137, resulting in high frequency ringing

in the transient response and loss of phase margin. One way to

minimize this effect is to place a small resistor in series with

each output to buffer the load capacitance. The resistor and load

capacitance will form a first-order, low-pass filter, so the resistor

value should be as small as possible. In some cases, the ADCs

require small series resistors to be added on their inputs.

Figure 39 and Figure 42 illustrate transient response versus ca-

pacitive load, and were generated using series resistors in each

output and a differential capacitive load.

Layout Considerations

Standard high speed PCB layout practices should be adhered to

when designing with the AD8137. A solid ground plane is

recommended and good wideband power supply decoupling

networks should be placed as close as possible to the supply pins.

To minimize stray capacitance at the summing nodes, the

copper in all layers under all traces and pads that connect to the

summing nodes should be removed. Small amounts of stray

summing-node capacitance will cause peaking in the frequency

response, and large amounts can cause instability. If some stray

summing-node capacitance is unavoidable, its effects can be

compensated for by placing small capacitors across the feedback

resistors.

Terminating a Single-Ended Input

Controlled impedance interconnections are used in most high

speed signal applications, and they require at least one line ter-

mination. In analog applications, a matched resistive termina-

tion is generally placed at the load end of the line. This section

deals with how to properly terminate a single-ended input to

the AD8137.

The input resistance presented by the AD8137 input circuitry is

seen in parallel with the termination resistor, and its loading

effect must be taken into account. The Thevenin equivalent

circuit of the driver, its source resistance, and the termination

resistance must all be included in the calculation as well. An

exact solution to the problem requires solution of several simul-

taneous algebraic equations and is beyond the scope of this data

sheet. An iterative solution is also possible and is simpler,

especially considering the fact that standard resistor values are

generally used.

Figure 66 shows the AD8137 in a unity-gain configuration, and

with the following discussion, provides a good example of how

to provide a proper termination in a 50 Ω environment.

Rev. A | Page 21 of 24

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