AD7934-6 Ver la hoja de datos (PDF) - Analog Devices

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AD7934-6

4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer

Analog Devices 

AD7934-6

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD 1

W/B 2

DB0 3

DB1 4

DB2 5

DB3 6

DB4 7

DB5 8

DB6 9

DB7 10

VDRIVE 11

DGND 12

DB8/HBEN 13

DB9 14

AD7934-6

TOP VIEW

(Not to Scale)

28 VIN3

27 VIN2

26 VIN1

25 VIN0

24 VREFIN/VREFOUT

23 AGND

22 CS

21 RD

20 WR

19 CONVST

18 CLKIN

17 BUSY

16 DB11

15 DB10

Figure 2.

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

VDD

Power Supply Input. The VDD range for the AD7934-6 is from 2.7 V to 5.25 V. The supply should be decoupled

to AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor.

2

W/B

Word/Byte Input. When this input is logic high, word transfer mode is enabled, and data is transferred to and

from the AD7934-6 in 12-bit words on Pin DB0 to Pin DB11. When W/B is logic low, byte transfer mode is

enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN

functionality. When operating in byte transfer mode, unused data lines should be tied off to DGND.

3 to 10

11

12

DB0 to DB7

VDRIVE

DGND

Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result, and allow the

control register to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage

levels for these pins are determined by the VDRIVE input.

Logic Power Supply Input. The voltage supplied at this pin determines what voltage the parallel interface of

the AD7934-6 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that

at VDD, but should never exceed VDD by more than 0.3 V.

Digital Ground. This is the ground reference point for all digital circuitry on the AD7934-6. This pin should

connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same

potential, and must not be more than 0.3 V apart, even on a transient basis.

13

DB8/HBEN

Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is

controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low,

the low byte of data written to or read from the AD7934-6 is on DB0 to DB7. When HBEN is high, the top four

bits of the data being written to or read from the AD7934-6 are on DB0 to DB3. When reading from the device,

DB4 and DB5 of the high byte contain the ID of the channel corresponding to the conversion result (see the

channel address bits in Table 9). DB6 and DB7 are always 0. When writing to the device, DB4 to DB7 of the

high byte must all be 0s.

14 to 16

17

DB9 to DB11

BUSY

Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the

control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic

high/low voltage levels for these pins are determined by the VDRIVE input.

Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the

falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete

and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track

mode just prior to the falling edge of BUSY, on the 13th rising edge of CLKIN (see Figure 34).

18

CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the

AD7934-6 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the

conversion time and achievable throughput rate. The CLKIN signal can be a continuous or burst clock.

19

CONVST

Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes

from track to hold mode on the falling edge of CONVST, and the conversion process is initiated at this point.

Following power-down, when operating in the autoshutdown or autostandby mode, a rising edge on

CONVST is used to power up the device.

20

WR

Write Input. Active low logic input used in conjunction with CS to write data to the control register.

21

RD

Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion

result is placed on the data bus following the falling edge of RD read while CS is low.

Rev. B | Page 7 of 28

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