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AD7755

Energy Metering IC with Pulse Output

Analog Devices 

AD7755

Figure 25 shows two typical connections for Channel V2. The

first option uses a PT (potential transformer) to provide com-

plete isolation from the mains voltage. In the second option the

AD7755 is biased around the neutral wire, and a resistor divider

is used to provide a voltage signal that is proportional to the line

voltage. Adjusting the ratio of Ra, Rb and VR is also a conve-

nient way of carrying out a gain calibration on the meter.

CT

Rf

PHASE NEUTRAL

؎660mV

Rf

AGND

V2P

Cf

V2N

Cf

Ra*

Cf

Rb*

VR*

؎660mV

PHASE NEUTRAL

*Ra >> Rb + VR

*Rb + VR = Rf

V2P

Rf

V2N

Cf

Figure 25. Typical Connections for Channel 2

POWER SUPPLY MONITOR

The AD7755 contains an on-chip power supply monitor. The

Analog Supply (AVDD) is continuously monitored by the AD7755.

If the supply is less than 4 V ± 5%, the AD7755 will be reset.

This is useful to ensure correct device start-up at power-up and

power-down. The power supply monitor has built in hysteresis

and filtering. This gives a high degree of immunity to false trig-

gering due to noisy supplies.

As can be seen from Figure 26, the trigger level is nominally set

at 4 V. The tolerance on this trigger level is about ± 5%. The

power supply and decoupling for the part should be such that

the ripple at AVDD does not exceed 5 V ± 5% as specified for

normal operation.

AVDD

5V

4V

0V

TIME

HPF and Offset Effects

Figure 27 shows the effect of offsets on the real power calcula-

tion. As can be seen, an offset on Channel 1 and Channel 2 will

contribute a dc component after multiplication. Since this dc

component is extracted by the LPF and used to generate the

real power information, the offsets will have contributed a con-

stant error to the real power calculation. This problem is easily

avoided by enabling the HPF (i.e., pin AC/DC is set logic high)

in Channel 1. By removing the offset from at least one channel,

no error component can be generated at dc by the multiplica-

tion. Error terms at cos(ωt) are removed by the LPF and the

digital-to-frequency conversion—see Digital-to-Frequency

Conversion section.

{ } { } ( ) ( ) Vcos ωt + VOS × Icos ωt + IOS =

( ) ( ) V

×

2

I

+ VOS

×

IOS

+ VOS

×

I cos

ωt

+ IOS × Vcos ωt

( ) +V × I × cos 2ωt

2

VOS ؋ IOS

V؋I

2

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL

POWER CALCULATION

IOS ؋ V

VOS ؋ I

0

␻

2␻

FREQUENCY – RAD/S

Figure 27. Effect of Channel Offset on the Real Power

Calculation

The HPF in Channel 1 has an associated phase response that is

compensated for on-chip. The phase compensation is activated

when the HPF is enabled and is disabled when the HPF is not

activated. Figures 28 and 29 show the phase error between

channels with the compensation network activated. The AD7755

is phase compensated up to 1 kHz as shown. This will ensure

correct active harmonic power calculation even at low power

factors.

INTERNAL

RESET RESET

ACTIVE

RESET

Figure 26. On-Chip Power Supply Monitor

–12–

REV. B

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