AD5539 Ver la hoja de datos (PDF) - Analog Devices
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AD5539 Datasheet PDF : 16 Pages
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AD5539
APPLICATIONS SUMMARY CHART
R1
R21
RLAG
CLAG2
CLEAD2
GAIN
Gain = –1 to –5
Circuit of Fig. 17
R2
G
2k
( ) ≤ R1
≥
1
4 R1 – 1
2 π 44 × 106 RLAG
3 pF
≈
G
–2
R2
Gain = –1 to –5
Circuit of Fig. 23
R2
R1
1
3 pF
G
2k
( ) ≤
≥
4 R1 – 1
2 π 44 × 106 RLAG
≈
G
–2
R2
Gain = +2 to +53
Circuit of Fig. 27
R2
R1
1
3 pF
G –1 2 k
( ) ≤
≥
10 R1 – 1
2 π 44 × 106 RLAG
≈ G –1
+3
R2
Gain = +2 to +54
Circuit of Fig. 29
R2
G –1 2 k
≤ R1
R1
NA
10 – 1
R2
3 pF
≈ G – 1 +3
Gain < –5
R2
1.5 k
NA
G
NA
Trimmer5 –20
Gain > +5
R2
G – 1 1.5 k
NA
NA
Trimmer5 +20
NOTES
G = Gain NA = Not Applicable
1Values given for specific results summarized here—applications can be adapted for values different than those specified.
2It is recommended that CLEAD and CLAG be trimmers covering a range that includes the computed value above.
3RSOURCE ≥ 200 Ω.
4RSOURCE ≥ 50 Ω.
5Use Voltronics CPA2 0.1–2.5 pF Teflon Trimmer Capacitor (or equivalent).
GAIN
FLATNESS
(TRIMMED)
± 0.2 dB
± 1 dB
± 1 dB
± 0.5 dB
± 0.2 dB
± 0.2 dB
3 dB
BANDWIDTH
200 MHz
180 MHz
390 MHz
340 MHz
80 MHz
80 MHz
The photos of Figures 40 and 41 demonstrate how the AD5539
easily settles to 1% (1 mV) in less than 12 ns; settling to 0.1%
(100 µV) requires less than 25 ns.
Figure 40. Error Signal from AD5539 Settling Time Test
Circuit – Falling Edge. Vertical Scale: 5 ns/div.; Horizontal
Scale: 500 µV/div
Figure 41. Error Signal from AD5539 Settling Time Test
Circuit – Rising Edge. Vertical Scale: 5 ns/div.; Horizontal
Scale: 500 µV/div
REV. B
–13–
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